Re: [PATCH v6 00/26] perf arm64: Support data type profiling

[Namhyung Kim <namhyung@kernel.org>]

On Sat, Sep 19, 2026 at 08:22:01AM -0300, Arnaldo Melo wrote:
> 
> 
> On September 19, 2026 4:10:46 AM GMT-03:00, Namhyung Kim <namhyung@kernel.org> wrote:
> >Hello,
> >
> >On Wed, Sep 16, 2026 at 01:29:14AM +0000, Tengda Wu wrote:
> >> This patch series implements data type profiling support for arm64,
> >> enabling 'perf annotate --data-type' to resolve memory locations and
> >> variable types on arm64 platforms.
> >> 
> >> The main changes since v5 include:
> >> v5: https://lore.kernel.org/all/cover.1788872630.git.wutengda@huaweicloud.com/
> >> 
> >> * __get_dwarf_regnum_arm64 optimization: compute directly based on character
> >>   judgment, avoiding strtol calls. (Ian Rogers)
> >> 
> >> * extract_op_location_arm64 issue fix: support parsing instructions such as
> >>   'cmp x0, x1, lsl #3'.
> >> 
> >> * Instruction tracking part, fixing issues pointed out by Sashiko, including:
> >>   - adding TSR_KIND_POINTER handling for ldr.
> >>   - premature returns in add and ldr causing percpu handling to be skipped.
> >>   - adding a reg != -1 check for stack type propagation, etc.
> >> 
> >> Patch organization
> >> ==================
> >> 
> >> The series is organized as follows:
> >> 
> >> 1. Fix disassembly mismatches (Patches 01-02)
> >>    Current perf annotate supports three disassembly backends: llvm,
> >>    capstone, and objdump. On arm64, inconsistencies between the output
> >>    of these backends (specifically llvm/capstone vs. objdump) often
> >>    prevent the tracker from correctly identifying registers and offsets.
> >>    These patches resolve these mismatches, ensuring consistent instruction
> >>    parsing across all supported backends.
> >> 
> >> 2. Infrastructure for arm64 operand parsing (Patches 03-09)
> >>    These patches establish the necessary infrastructure for arm64-specific
> >>    operand handling. This includes implementing new callbacks and data
> >>    structures to manage arm64's unique addressing modes and register sets.
> >>    This foundation is essential for the subsequent type-tracking logic.
> >> 
> >> 3. ARM SPE event handling (Patches 10-11)
> >>    Patch 10 automatically deduplicates overlapping ARM SPE events (e.g.,
> >>    l1d-miss, tlb-access) in 'perf annotate' by retaining only the
> >>    "instructions" event when data type profiling is enabled. Patch 11
> >>    defaults  the synthesized event period to 1 for ARM SPE to fix zero
> >>    'Percent' values in annotate output.
> >
> >Thanks for working on this!
> >
> >I think it's ready to merge up to this point. 
> 
> You mean patches 1-11? 

Yes.

Thanks,
Namhyung