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Tue, 15 Sep 2026 02:35:03 -0700 (PDT) Received: from sifive.com ([136.226.240.165]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-cc4c6549d95sm6303718a12.12.2026.09.15.02.35.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 02:35:02 -0700 (PDT) Date: Tue, 15 Sep 2026 17:34:58 +0800 From: Max Chou To: Chao Liu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, richard.henderson@linaro.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: Re: [PATCH 3/6] tests/tcg/riscv64: Add vector masked fault-only-first PMP test Message-ID: References: <20260909084154.223529-1-max.chou@sifive.com> <20260909084154.223529-4-max.chou@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:3b::10; envelope-from=max.chou@sifive.com; helo=mail-pz2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026-09-11 13:49, Chao Liu wrote: > Hi Max, > > On Wed, Sep 09, 2026 at 04:41:50PM +0800, Max Chou wrote: > > Add a bare-metal test for masked vector fault-only-first loads across > > locked NA4 PMP regions inside one page. The test covers masked-off > > elements, a faulting active element 0, and later active faults that > > shorten vl. > > > > Signed-off-by: Max Chou > > --- > > tests/tcg/riscv64/Makefile.softmmu-target | 13 ++ > > tests/tcg/riscv64/rvv-ldst.inc | 91 ++++++++ > > tests/tcg/riscv64/test-rvv-ldst-ff-pmp.S | 259 ++++++++++++++++++++++ > > 3 files changed, 363 insertions(+) > > create mode 100644 tests/tcg/riscv64/rvv-ldst.inc > > create mode 100644 tests/tcg/riscv64/test-rvv-ldst-ff-pmp.S > > > > diff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target > > index f2c75abd57a..0fdf242f735 100644 > > --- a/tests/tcg/riscv64/Makefile.softmmu-target > > +++ b/tests/tcg/riscv64/Makefile.softmmu-target > > @@ -85,5 +85,18 @@ run-test-vle32ff: test-vle32ff > > $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true $(QEMU_OPTS)$<) > > test-vle32ff: CFLAGS += -march=rv64gcv > > > > +RVV_LDST_MARCH = -march=rv64gcv > > +RVV_LDST_TESTS = test-rvv-ldst-ff-pmp > > +CLEANFILES += $(RVV_LDST_TESTS) > > + > > +$(RVV_LDST_TESTS): %: %.S rvv-ldst.inc $(LINK_SCRIPT) > > + $(CC) $(CFLAGS) $(RVV_LDST_MARCH) $< -Wa,--noexecstack -c -o $@.o > > + $(LD) $(LDFLAGS) $@.o -o $@ > > + > > +EXTRA_RUNS += run-test-rvv-ldst-ff-pmp > > + > > +run-test-rvv-ldst-ff-pmp: test-rvv-ldst-ff-pmp > > + $(call run-test, $<, $(QEMU) -cpu rv64$(comma)v=true$(comma)vlen=128$(comma)elen=64$(comma)vext_spec=v1.0$(comma)rvv_ta_all_1s=true$(comma)rvv_ma_all_1s=true $(QEMU_OPTS)$<) > > + > Just a heads-up, TCG tests are moving to Meson build, so this needs to be > based on: > > https://lore.kernel.org/qemu-devel/20260818192309.22169-1-pierrick.bouvier@oss.qualcomm.com/ > > Thanks, > Chao Hi Chao, Thanks for the information. Daniel also shared the same information to me.I will send v2 for this TCG test build flow. Thanks, rnax