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Tue, 15 Sep 2026 02:47:10 -0700 (PDT) Received: from sifive.com ([136.226.240.165]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-86b29abc4basm5799242b3a.39.2026.09.15.02.47.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 02:47:09 -0700 (PDT) Date: Tue, 15 Sep 2026 17:47:06 +0800 From: Max Chou To: Richard Henderson Cc: qemu-devel@nongnu.org, palmer@dabbelt.com, daniel.barboza@oss.qualcomm.com, Alistair.Francis@wdc.com, philmd@oss.qualcomm.com Subject: Re: [PATCH v3 00/11] tcg/riscv64: Fix AUIPC pair range validation Message-ID: References: <20260914000814.785155-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260914000814.785155-1-richard.henderson@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:3b::f; envelope-from=max.chou@sifive.com; helo=mail-pz2-x0f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026-09-13 14:08, Richard Henderson wrote: > Hi Max, > > In v2, the change from int32_t to uint32_t is pretty much > the opposite of what should have been done, since all of > these are logically signed values. I've adjusted all of > the encoders to take signed inputs and assert in range. > > In the process, I noticed tha the branch range tests were > off by one. Now all performed in exactly one place. > > Finally, tcg_out_ldst needed updates for AUIPC as well. > > I've tested this lightly so far; full testing on a rather > slow riscv machine is still on-going. > Hi Richard, Thank you for the v3 patchset series. I’m currently reviewing and trying to test it in my environment. Could you please let me know what full testing you used to test this patchset? Thanks, rnax > > r~ > > > Max Chou (2): > tcg/riscv64: Validate AUIPC relocation range > tcg/riscv64: Fall back when AUIPC pairs are out of range > > Richard Henderson (9): > tcg/riscv64: Return tcg_insn_unit from insn encoders > tcg/riscv64: Rename sb-type to b-type format > tcg/riscv64: Rename uj-type to j-type format > tcg/riscv64: Use signed type for encoding immediates > tcg/riscv64: Adjust sign of lui immediate in tcg_out_movi > tcg/riscv64: Assert immediate in range for [isu]-type insns > tcg/riscv64: Return success from encode_jimm > tcg/riscv64: Return success from encode_bimm > tcg/riscv64: Fix off-by-one in branch range tests > > tcg/riscv64/tcg-target.c.inc | 230 ++++++++++++++++++----------------- > 1 file changed, 121 insertions(+), 109 deletions(-) > > -- > 2.53.0 >