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Wed, 16 Sep 2026 01:30:39 +0000 Date: Tue, 15 Sep 2026 18:30:34 -0700 From: Alison Schofield To: Anisa Su CC: , , , , , , , , , Ira Weiny , Anisa Su , Wonjae Lee , Junhee Park , Heesoo Kim Subject: Re: [RESEND PATCH v13 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Message-ID: References: <20260908102124.2231730-2-anisa.su@samsung.com> <20260908102124.2231730-5-anisa.su@samsung.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260908102124.2231730-5-anisa.su@samsung.com> X-ClientProxiedBy: SJ0PR13CA0176.namprd13.prod.outlook.com (2603:10b6:a03:2c7::31) To DS4PPF0BAC23327.namprd11.prod.outlook.com (2603:10b6:f:fc02::9) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS4PPF0BAC23327:EE_|DS0PR11MB7736:EE_ X-MS-Office365-Filtering-Correlation-Id: db2f05b1-5f63-4d84-2ff0-08df13921d4a X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|23010399003|18002099003|22082099003|10067099003|11063799006|5023799004|4143699003|56012099006; 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With Richard's comment addressed, you can add: Reviewed-by: Alison Schofield > > Signed-off-by: Ira Weiny > Co-developed-by: Anisa Su > Signed-off-by: Anisa Su > Tested-by: Wonjae Lee > Tested-by: Junhee Park > Tested-by: Heesoo Kim > > --- > Changes: > 1. cdat.c: set found=true as soon as a partition contains the range, and > break out of the search on a DSMAD handle mismatch. Partitions are > disjoint, so the continue could never match another one; the search > always ran out and the entry was reported twice, once as a mismatch > and again as "no partition for dsmas dpa" even though a partition did > cover it. > > 2. cdat.c: only assign shareable for the dynamic ram 1 partition. It > was set for every partition the DSMAS range fell into, while the > handle check above it is DC only. The field describes a DC partition, > so ram and pmem have no use for it. > > 3. Commit message: drop the claim that the read only attribute is > gathered. Only the shareable flag is. Nothing in this series or the > follow-on DCD work consumes a read only flag, so storing it would be > dead state. Implementing read-only (reject writes to RO partitions) > applies to any DSMAS described range, non-specific to dynamic capacity and > belongs to separate patch. > --- > drivers/cxl/core/cdat.c | 32 +++++++++++++++++++++++++------- > drivers/cxl/core/hdm.c | 1 + > drivers/cxl/core/mbox.c | 9 +++++++++ > drivers/cxl/core/memdev.c | 17 ++++++++++------- > drivers/cxl/cxlmem.h | 2 ++ > include/cxl/cxl.h | 4 ++++ > 6 files changed, 51 insertions(+), 14 deletions(-) > > diff --git a/drivers/cxl/core/cdat.c b/drivers/cxl/core/cdat.c > index 5c9f07262513..05058d4520f2 100644 > --- a/drivers/cxl/core/cdat.c > +++ b/drivers/cxl/core/cdat.c > @@ -17,6 +17,7 @@ struct dsmas_entry { > struct access_coordinate cdat_coord[ACCESS_COORDINATE_MAX]; > int entries; > int qos_class; > + bool shareable; > }; > > static u32 cdat_normalize(u16 entry, u64 base, u8 type) > @@ -74,6 +75,8 @@ static int cdat_dsmas_handler(union acpi_subtable_headers *header, void *arg, > return -ENOMEM; > > dent->handle = dsmas->dsmad_handle; > + /* Shareable is CDAT 1.03 and later, DSMAS Flags bit 3 */ > + dent->shareable = dsmas->flags & ACPI_CDAT_DSMAS_SHAREABLE; > dent->dpa_range.start = le64_to_cpu((__force __le64)dsmas->dpa_base_address); > dent->dpa_range.end = le64_to_cpu((__force __le64)dsmas->dpa_base_address) + > le64_to_cpu((__force __le64)dsmas->dpa_length) - 1; > @@ -266,18 +269,33 @@ static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds, > bool found = false; > > for (int i = 0; i < cxlds->nr_partitions; i++) { > - struct resource *res = &cxlds->part[i].res; > + struct cxl_dpa_partition *part = &cxlds->part[i]; > struct range range = { > - .start = res->start, > - .end = res->end, > + .start = part->res.start, > + .end = part->res.end, > }; > > - if (range_contains(&range, &dent->dpa_range)) { > - update_perf_entry(dev, dent, > - &cxlds->part[i].perf); > - found = true; > + if (!range_contains(&range, &dent->dpa_range)) > + continue; > + > + found = true; > + /* > + * part->handle is from Get DC Config, dent->handle > + * from the CDAT DSMAS entry. > + */ > + if (part->mode == CXL_PARTMODE_DYNAMIC_RAM_1 && > + dent->handle != part->handle) { > + dev_warn(dev, > + "DSMAD handle mismatch: %pra has %u, DSMAS %pra has %u\n", > + &range, part->handle, > + &dent->dpa_range, dent->handle); > break; > } > + > + update_perf_entry(dev, dent, &part->perf); > + if (part->mode == CXL_PARTMODE_DYNAMIC_RAM_1) > + part->shareable = dent->shareable; > + break; > } > > if (!found) > diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c > index 0ef076c08ed2..7f63b86887f4 100644 > --- a/drivers/cxl/core/hdm.c > +++ b/drivers/cxl/core/hdm.c > @@ -477,6 +477,7 @@ int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info) > > cxlds->part[i].perf.qos_class = CXL_QOS_CLASS_INVALID; > cxlds->part[i].mode = part->mode; > + cxlds->part[i].handle = part->handle; > > /* Require ordered + contiguous partitions */ > if (i) { > diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c > index a484e23b2b3a..efc3bf3563a5 100644 > --- a/drivers/cxl/core/mbox.c > +++ b/drivers/cxl/core/mbox.c > @@ -1365,6 +1365,7 @@ static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part, > { > u64 blk_size = le64_to_cpu(dev_part->block_size); > u64 len = le64_to_cpu(dev_part->length); > + u32 handle = le32_to_cpu(dev_part->dsmad_handle); > > /* > * Not an error; leave the entry empty. A partially zeroed partition > @@ -1376,9 +1377,17 @@ static int cxl_dc_check(struct device *dev, struct cxl_dc_partition_info *part, > return 0; > } > > + /* The CDAT DSMAD handle this refers to is 8 bits */ > + if (handle & ~0xFF) { > + dev_warn(dev, "DSMAD handle 0x%x exceeds the 8 bit CDAT DSMAD handle\n", > + handle); > + return -EINVAL; > + } > + > *part = (struct cxl_dc_partition_info) { > .start = le64_to_cpu(dev_part->base), > .size = le64_to_cpu(dev_part->decode_length) * CXL_CAPACITY_MULTIPLIER, > + .handle = handle, > }; > > /* > diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c > index fdd6b395dcdf..4a5793fa3cbf 100644 > --- a/drivers/cxl/core/memdev.c > +++ b/drivers/cxl/core/memdev.c > @@ -594,7 +594,8 @@ bool is_cxl_memdev(const struct device *dev) > } > EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, "CXL"); > > -static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_partition_mode mode) > +static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, > + enum cxl_partition_mode mode, u8 handle) > { > int i = info->nr_partitions; > > @@ -606,6 +607,7 @@ static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_pa > .end = start + size - 1, > }; > info->part[i].mode = mode; > + info->part[i].handle = handle; > info->nr_partitions++; > } > > @@ -623,9 +625,9 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info) > info->size = mds->total_bytes; > > if (mds->partition_align_bytes == 0) { > - add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM); > + add_part(info, 0, mds->volatile_only_bytes, CXL_PARTMODE_RAM, 0); > add_part(info, mds->volatile_only_bytes, > - mds->persistent_only_bytes, CXL_PARTMODE_PMEM); > + mds->persistent_only_bytes, CXL_PARTMODE_PMEM, 0); > return 0; > } > > @@ -635,9 +637,9 @@ int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info) > return rc; > } > > - add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM); > + add_part(info, 0, mds->active_volatile_bytes, CXL_PARTMODE_RAM, 0); > add_part(info, mds->active_volatile_bytes, mds->active_persistent_bytes, > - CXL_PARTMODE_PMEM); > + CXL_PARTMODE_PMEM, 0); > > return 0; > } > @@ -674,7 +676,8 @@ int cxl_configure_dcd(struct cxl_memdev_state *mds, struct cxl_dpa_info *info) > info->size += dc_info.size; > dev_dbg(dev, "Adding dynamic ram partition 1; %#llx size %#llx\n", > dc_info.start, dc_info.size); > - add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM_1); > + add_part(info, dc_info.start, dc_info.size, CXL_PARTMODE_DYNAMIC_RAM_1, > + dc_info.handle); > > return 0; > } > @@ -693,7 +696,7 @@ int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity) > .size = capacity, > }; > > - add_part(&range_info, 0, capacity, CXL_PARTMODE_RAM); > + add_part(&range_info, 0, capacity, CXL_PARTMODE_RAM, 0); > return cxl_dpa_setup(cxlds, &range_info); > } > EXPORT_SYMBOL_NS_GPL(cxl_set_capacity, "CXL"); > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index 4fac65dbb808..9fd5af2e41d4 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -140,6 +140,7 @@ struct cxl_dpa_info { > struct cxl_dpa_part_info { > struct range range; > enum cxl_partition_mode mode; > + u8 handle; > } part[CXL_NR_PARTITIONS_MAX]; > int nr_partitions; > }; > @@ -851,6 +852,7 @@ int cxl_dev_state_identify(struct cxl_memdev_state *mds); > struct cxl_dc_partition_info { > u64 start; > u64 size; > + u8 handle; > }; > > int cxl_dev_dc_identify(struct cxl_mailbox *mbox, > diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h > index 4ef9511fbbdd..43edcde5bce3 100644 > --- a/include/cxl/cxl.h > +++ b/include/cxl/cxl.h > @@ -141,11 +141,15 @@ enum cxl_partition_mode { > * @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res) > * @perf: performance attributes of the partition from CDAT > * @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic... > + * @handle: DSMAS handle that represents this partition > + * @shareable: Is the partition shareable (from its CDAT DSMAS entry) > */ > struct cxl_dpa_partition { > struct resource res; > struct cxl_dpa_perf perf; > enum cxl_partition_mode mode; > + u8 handle; > + bool shareable; > }; > > #define CXL_NR_PARTITIONS_MAX 3 > -- > 2.43.0 >