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Wed, 30 Sep 2026 16:03:57 -0700 Received: from nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Wed, 30 Sep 2026 16:03:57 -0700 Date: Wed, 30 Sep 2026 16:03:53 -0700 From: Nicolin Chen To: Daniel Mentz CC: , Will Deacon , Mostafa Saleh Subject: Re: [PATCH] iommu/arm-smmu-v3: Align memory attributes for SMMU-originated accesses Message-ID: References: <20260929032229.3532247-1-danielmentz@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260929032229.3532247-1-danielmentz@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E83:EE_|CY5PR12MB6478:EE_ X-MS-Office365-Filtering-Correlation-Id: 575925d1-a813-40f2-4419-08df1f472218 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|82310400026|376014|36860700016|18002099003|22082099003|10067099003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4DRBccPS2Kdh7Kt31wfO7sP9psMwv1Bqi/ZHsmuSEa+BQe79jpV2o9bo/n4aqjRpPpK8ootKD/UMuLT7ONONSPIl2HqlX6Hzj3Z47wVymRW4NDsFmPycY83b+W/0m+s+3fFp5ktnJCRsRbRjYabD/AKIeTXGVsZpUHgXt/pQ2rSkis4gpCHRu//qAU1wYywS3Qh/OqycKYlis0uWYUaBbfl1hghKNxn87DWaT2Bbpz6zRWfraOops/Nb3s41MHLi0oOC/Ls5hC4KcFZKdP4KgGENjr7dsjJEcTWVePs4hwmIZ8bwpFhZNyQXAeSfERokhZl87vM4BBD1SxxeNsWuGVH4oyuvS++TIKqaRtBcfzkVy4Y5k9xsAS6zWdrN1HsKjlxVWoAOXZO+SynAacuWhFEsrTykRSr2/6X9wGCNRoIz3S2vpq0M7AFIO/5URsgH X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 23:04:08.4325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 575925d1-a813-40f2-4419-08df1f472218 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E83.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6478 On Tue, Sep 29, 2026 at 03:22:29AM +0000, Daniel Mentz wrote: > @@ -4858,12 +4867,20 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > return ret; > > /* CR1 (table and queue memory attributes) */ > - reg = FIELD_PREP(CR1_TABLE_SH, ARM_SMMU_SH_ISH) | > - FIELD_PREP(CR1_TABLE_OC, CR1_CACHE_WB) | > - FIELD_PREP(CR1_TABLE_IC, CR1_CACHE_WB) | > - FIELD_PREP(CR1_QUEUE_SH, ARM_SMMU_SH_ISH) | > - FIELD_PREP(CR1_QUEUE_OC, CR1_CACHE_WB) | > - FIELD_PREP(CR1_QUEUE_IC, CR1_CACHE_WB); > + if (smmu->features & ARM_SMMU_FEAT_COHERENCY) { > + cache = CR1_CACHE_WB; > + sh = ARM_SMMU_SH_ISH; > + } else { > + cache = CR1_CACHE_NC; > + sh = ARM_SMMU_SH_OSH; > + } > + > + reg = FIELD_PREP(CR1_TABLE_SH, sh) | > + FIELD_PREP(CR1_TABLE_OC, cache) | > + FIELD_PREP(CR1_TABLE_IC, cache) | > + FIELD_PREP(CR1_QUEUE_SH, sh) | > + FIELD_PREP(CR1_QUEUE_OC, cache) | > + FIELD_PREP(CR1_QUEUE_IC, cache); > writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); Nit: this is a big function. Perhaps, cr1_sh and cr1_cache? Otherwise, Reviewed-by: Nicolin Chen