Re: [PATCH v2] PCI: tegra264: Fix Link Capabilities register offset

[Thierry Reding <thierry.reding@kernel.org>]

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On Wed, Sep 23, 2026 at 02:57:20PM -0500, Bjorn Helgaas wrote:
> The PCI Express Capability begins at 0x48.  Link Capabilities is a 32-bit
> register at offset 0xc, and Link Status is a 16-bit register at offset
> 0x12:
> 
>   Link Capabilities is at 0x48 + 0xc  = 0x54
>   Link Status       is at 0x48 + 0x12 = 0x5a
> 
> Previously the driver read Link Capabilities with a 16-bit read from
> XTL_RC_PCIE_CFG_LINK_CAPS (0x56), which incorrectly read just the upper
> half of the register.  When a hotplug-capable port has no link during
> probe, tegra264_pcie_icc_set() consequently derives the maximum speed and
> width from unrelated bits and requests the wrong interconnect bandwidth.
> 
> Correct the Link Capabilities usage by adding a XTL_RC_PCIE_CAP definition
> for the base of the PCIe Capability, using the existing PCI_EXP_LNKCAP
> (0xc) and PCI_EXP_LNKSTA (0x12) offsets so they're easily searchable, and
> reading the entire 32 bits of Link Capabilities.
> 
> Fixes: 01c3c27a0ef6 ("PCI: tegra264: Add Tegra264 support")
> Based-on-patch-by: Linmao Li <lilinmao@kylinos.cn>
> Link: https://lore.kernel.org/20260827093919.2825467-1-lilinmao@kylinos.cn
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> 
> This fixes a real bug, so I'd like to get this in pci/next for v7.4.  I
> can't test this though, so need a review and test from somebody with the
> hardware.
> 
>  drivers/pci/controller/pcie-tegra264.c | 9 ++++-----
>  1 file changed, 4 insertions(+), 5 deletions(-)

Sorry for the late reply, I had missed the patch you sent out. I've run
this on the Jetson AGX Thor DevKit and it still boots fine, all the PCI
devices show up:

Tested-by: Thierry Reding <treding@nvidia.com>

Also, the offsets do match what the register documentation says, so:

Reviewed-by: Thierry Reding <treding@nvidia.com>

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