From: "Nuno Sá" <nuno.sa@analog.com>
To: Mark Brown <broonie@kernel.org>
Cc: "Nuno Sá" <noname.nuno@gmail.com>,
"Jonathan Santos" <Jonathan.Santos@analog.com>,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
dlechner@baylibre.com, michael.hennerich@analog.com,
jonath4nns@gmail.com, andriy.shevchenko@intel.com
Subject: Re: [PATCH v2 2/2] spi: axi-spi-engine: fix stale SYNC IRQ pending in trigger_enable
Date: Thu, 1 Oct 2026 13:24:33 +0100 [thread overview]
Message-ID: <ar5QVsQs2yrPqdxI@nsa> (raw)
In-Reply-To: <f0b918c9-2ede-4ff6-9ccf-6b819b972f38@sirena.org.uk>
On Thu, Oct 01, 2026 at 12:58:52PM +0100, Mark Brown wrote:
> On Thu, Oct 01, 2026 at 07:55:45AM +0100, Nuno Sá wrote:
> > On Wed, 2026-09-30 at 14:09 +0100, Mark Brown wrote:
>
> > > I'm not seeing anything here for the issue with ensuring posted writes
> > > are completed before we drop the lock? The write may not be visible on
> > > enother CPU, we need a read from the controller or something.
>
> > Just for my understanding, why would it be an issue? The trigger register seems to
> > only be accessible from the trigger callbacks which are protected by a lock where we
> > have implied barriers. Im sure I'm missing what can go wrong here :)
>
> Are you sure that's true for mutexes? I thought they only covered
> memory, not device stuff, but ICBW.
Oh right, likely not a full barrier
- Nuno Sá
next prev parent reply other threads:[~2026-10-01 12:23 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 2:17 [PATCH v2 0/2] spi: axi-spi-engine: fix stale SYNC IRQ pending Jonathan Santos
2026-09-30 2:17 ` [PATCH v2 1/2] " Jonathan Santos
2026-09-30 2:17 ` [PATCH v2 2/2] spi: axi-spi-engine: fix stale SYNC IRQ pending in trigger_enable Jonathan Santos
2026-09-30 13:09 ` Mark Brown
2026-10-01 6:55 ` Nuno Sá
2026-10-01 11:58 ` Mark Brown
2026-10-01 12:24 ` Nuno Sá [this message]
2026-09-30 11:59 ` [PATCH v2 0/2] spi: axi-spi-engine: fix stale SYNC IRQ pending Nuno Sá
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