From: Sean Christopherson <seanjc@google.com>
To: Dongli Zhang <dongli.zhang@oracle.com>
Cc: Chao Gao <chao.gao@intel.com>,
kvm@vger.kernel.org, pbonzini@redhat.com, joe.jin@oracle.com
Subject: Re: [PATCH 1/1] KVM: x86: lapic: update apic_base and APIC ID together
Date: Mon, 21 Sep 2026 08:53:06 -0700 [thread overview]
Message-ID: <arFS4k_G3mukB-s9@google.com> (raw)
In-Reply-To: <ac24c392-c7bd-47dd-a055-ea5f46cbbca8@oracle.com>
On Wed, Aug 19, 2026, Dongli Zhang wrote:
> On Tue, Aug 18, 2026 10:48:18PM -0700, Chao Gao wrote:
> > So the goal is to avoid a _transient_ APICv inhibit in a corner case?
>
> Yes.
>
> >
> > If so, please spell out in the changelog why it's worth fixing.
>
> Regarding "why it's worth fixing," the primary motivation is to avoid
> unnecessary APICv inhibition and reactivation, ideally throughout the entire
> lifecycle of a VM.
That doesn't explain why it's worth fixing, that just explains what you're trying
to do. IMO, serializing xAPIC<=>x2APIC transitions across vCPUs and conditionally
taking a per-VM lock in vCPU context is not at all worth fixing a transient
condition that requires hitting a small timing window in a relatively rare, slow
path.
next prev parent reply other threads:[~2026-09-21 15:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-18 23:42 [PATCH 1/1] KVM: x86: lapic: update apic_base and APIC ID together Dongli Zhang
2026-08-18 23:49 ` Dongli Zhang
2026-08-19 0:03 ` sashiko-bot
2026-08-19 5:48 ` Chao Gao
2026-08-19 14:02 ` Dongli Zhang
2026-09-21 15:53 ` Sean Christopherson [this message]
-- strict thread matches above, loose matches on Subject: below --
2026-08-23 12:29 kernel test robot
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