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[34.127.87.210]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a0bda430b3sm5720254a91.0.2026.09.25.15.27.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 15:27:39 -0700 (PDT) Date: Fri, 25 Sep 2026 22:27:35 +0000 From: Samiullah Khawaja To: David Matlack Cc: Joerg Roedel , Will Deacon , Jason Gunthorpe , Robin Murphy , Kevin Tian , Alex Williamson , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Pasha Tatashin , Lu Baolu , Pranjal Shrivastava Subject: Re: [RFC PATCH 0/3] iommu/arm-smmu-v3: Add support for hitless replace of CD entries Message-ID: References: <20260925011308.3381953-1-skhawaja@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: On Fri, Sep 25, 2026 at 09:44:05PM +0000, David Matlack wrote: >On 2026-09-25 01:13 AM, Samiullah Khawaja wrote: >> This patch series adds support for replacing IOMMU domains with S1 page >> tables hitlessly, that is without disrupting the ongoing DMAs. This is >> one of the dependencies of the Liveupdate IOMMU support for Arm SMMUv3. >> >> S1 domains are programmed by CD entries in the CD table. During a new >> domain attach these are updated using arm_smmu_write_cd_entry(). Since >> ASID and TTB0 are in different 64-bit words, arm_smmu_write_cd_entry() >> considers it a non-hitless update and sets V=0. This means such an >> update is disruptive and would generate translation faults if there are >> ongoing DMAs. >> >> Replace the CD entries by using an unused temporary ASID in the >> following sequence to allow hitless replacement of CD entry, >> >> - Update the CD entry with temporary ASID. >> - Update the CD entry with the target TTB0. >> - Invalidate the temporary ASID. >> - Update the CD entry with target ASID. >> - Invalidate and release the temporary ASID. >> >> The series adds a vfio selftest that triggers a continuous DMA and does >> the hwpt replace while the DMA is ongoing. Since domain replacement is a >> race with the translation requests, the test does it multiple times to >> capture the small window where IOMMU faults can occur. >> >> Without this change we can observe the SMMU faults in the kernel logs >> and with it the SMMU faults do not occur. >> >> This is only tested on qemu with the emulated SMMUv3 and an out of tree >> NVMe vfio selftest driver, not on real hardware. Following are not >> covered and can be done later, > >Out of curiousity, does the in-tree VFIO selftests driver for IGB not >work for this testing scenario? I tried with the IGB driver first, but I couldn't get the DMAs to work. Its probably my setup, will recheck. Sami