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[35.203.150.192]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df91476bb4sm16242765ad.83.2026.09.25.14.44.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 14:44:14 -0700 (PDT) Date: Fri, 25 Sep 2026 21:44:05 +0000 From: David Matlack To: Samiullah Khawaja Cc: Joerg Roedel , Will Deacon , Jason Gunthorpe , Robin Murphy , Kevin Tian , Alex Williamson , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Pasha Tatashin , Lu Baolu , Pranjal Shrivastava Subject: Re: [RFC PATCH 0/3] iommu/arm-smmu-v3: Add support for hitless replace of CD entries Message-ID: References: <20260925011308.3381953-1-skhawaja@google.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260925011308.3381953-1-skhawaja@google.com> On 2026-09-25 01:13 AM, Samiullah Khawaja wrote: > This patch series adds support for replacing IOMMU domains with S1 page > tables hitlessly, that is without disrupting the ongoing DMAs. This is > one of the dependencies of the Liveupdate IOMMU support for Arm SMMUv3. > > S1 domains are programmed by CD entries in the CD table. During a new > domain attach these are updated using arm_smmu_write_cd_entry(). Since > ASID and TTB0 are in different 64-bit words, arm_smmu_write_cd_entry() > considers it a non-hitless update and sets V=0. This means such an > update is disruptive and would generate translation faults if there are > ongoing DMAs. > > Replace the CD entries by using an unused temporary ASID in the > following sequence to allow hitless replacement of CD entry, > > - Update the CD entry with temporary ASID. > - Update the CD entry with the target TTB0. > - Invalidate the temporary ASID. > - Update the CD entry with target ASID. > - Invalidate and release the temporary ASID. > > The series adds a vfio selftest that triggers a continuous DMA and does > the hwpt replace while the DMA is ongoing. Since domain replacement is a > race with the translation requests, the test does it multiple times to > capture the small window where IOMMU faults can occur. > > Without this change we can observe the SMMU faults in the kernel logs > and with it the SMMU faults do not occur. > > This is only tested on qemu with the emulated SMMUv3 and an out of tree > NVMe vfio selftest driver, not on real hardware. Following are not > covered and can be done later, Out of curiousity, does the in-tree VFIO selftests driver for IGB not work for this testing scenario?