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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Sep 27, 2026 at 04:25:29PM +0800, Max Chou wrote: > Add the CPU config properties for SiFive's custom int8 matrix > multiply vector extensions: > > - Xsfvqmaccdod: 2x8x2 int8 matrix-multiply-accumulate operations > - Xsfvqmaccqoq: 4x8x4 int8 matrix-multiply-accumulate operations > > All instructions of these extensions require the Zve32x extension > to be present whenever either extension is enabled. Validate this > in riscv_cpu_validate_vendor_ext() alongside the existing vector > extension validation in riscv_cpu_validate_set_extensions(). > > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Alistair Francis > Signed-off-by: Max Chou Reviewed-by: Chao Liu Thanks, Chao > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg_fields.h.inc | 2 ++ > target/riscv/tcg/tcg-cpu.c | 16 ++++++++++++++++ > 3 files changed, 20 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index da4c1a090b9..55833896bef 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -299,6 +299,8 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(xmipscbop, PRIV_VERSION_1_12_0, ext_xmipscbop), > ISA_EXT_DATA_ENTRY(xmipscmov, PRIV_VERSION_1_12_0, ext_xmipscmov), > ISA_EXT_DATA_ENTRY(xmipslsp, PRIV_VERSION_1_12_0, ext_xmipslsp), > + ISA_EXT_DATA_ENTRY(xsfvqmaccdod, PRIV_VERSION_1_13_0, ext_xsfvqmaccdod), > + ISA_EXT_DATA_ENTRY(xsfvqmaccqoq, PRIV_VERSION_1_13_0, ext_xsfvqmaccqoq), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc > index f91c780299c..0f3bda1331c 100644 > --- a/target/riscv/cpu_cfg_fields.h.inc > +++ b/target/riscv/cpu_cfg_fields.h.inc > @@ -159,6 +159,8 @@ BOOL_FIELD(ext_xmipscbop) > BOOL_FIELD(ext_xmipscmov) > BOOL_FIELD(ext_xmipslsp) > BOOL_FIELD(ext_xlrbr) > +BOOL_FIELD(ext_xsfvqmaccdod) > +BOOL_FIELD(ext_xsfvqmaccqoq) > > BOOL_FIELD(big_endian) > BOOL_FIELD(mmu) > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index b68160af830..4f132488b9e 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -416,6 +416,16 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, > } > } > > +static void riscv_cpu_validate_vendor_ext(RISCVCPU *cpu, Error **errp) > +{ > + if ((cpu->cfg.ext_xsfvqmaccdod || cpu->cfg.ext_xsfvqmaccqoq) && > + !cpu->cfg.ext_zve32x) { > + error_setg(errp, "Xsfvqmaccdod/Xsfvqmaccqoq extensions require " > + "Zve32x extension"); > + return; > + } > +} > + > static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > { > CPURISCVState *env = &cpu->env; > @@ -793,6 +803,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > return; > } > > + riscv_cpu_validate_vendor_ext(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { > error_setg(errp, "svukte is not supported for RV32"); > return; > -- > 2.43.0 >