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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Sep 27, 2026 at 04:25:30PM +0800, Max Chou wrote: > Every entry added to riscv_multi_ext_implied_rules currently has to > reflow whatever line it lands on, since entries are packed several > per line. List one rule per line instead so future additions are a > pure append. > > Suggested-by: Daniel Henrique Barboza > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Alistair Francis > Signed-off-by: Max Chou Reviewed-by: Chao Liu Thanks, Chao > --- > target/riscv/cpu.c | 58 +++++++++++++++++++++++++++++++++++----------- > 1 file changed, 44 insertions(+), 14 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 55833896bef..90fa1d714c7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2913,20 +2913,50 @@ RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = { > }; > > RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { > - &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED, > - &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED, > - &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED, > - &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED, > - &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED, > - &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED, > - &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, > - &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED, > - &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, > - &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, > - &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, > - &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SHA_IMPLIED, > - &SSCFG_IMPLIED, &SUPM_IMPLIED, &SSPM_IMPLIED, &SMCTR_IMPLIED, > - &SSCTR_IMPLIED, &SSSTATEEN_IMPLIED, > + &ZCB_IMPLIED, > + &ZCD_IMPLIED, > + &ZCE_IMPLIED, > + &ZCF_IMPLIED, > + &ZCMP_IMPLIED, > + &ZCMT_IMPLIED, > + &ZDINX_IMPLIED, > + &ZFA_IMPLIED, > + &ZFBFMIN_IMPLIED, > + &ZFH_IMPLIED, > + &ZFHMIN_IMPLIED, > + &ZFINX_IMPLIED, > + &ZHINX_IMPLIED, > + &ZHINXMIN_IMPLIED, > + &ZICNTR_IMPLIED, > + &ZIHPM_IMPLIED, > + &ZK_IMPLIED, > + &ZKN_IMPLIED, > + &ZKS_IMPLIED, > + &ZVBB_IMPLIED, > + &ZVE32F_IMPLIED, > + &ZVE32X_IMPLIED, > + &ZVE64D_IMPLIED, > + &ZVE64F_IMPLIED, > + &ZVE64X_IMPLIED, > + &ZVFBFA_IMPLIED, > + &ZVFBFMIN_IMPLIED, > + &ZVFBFWMA_IMPLIED, > + &ZVFH_IMPLIED, > + &ZVFHMIN_IMPLIED, > + &ZVKN_IMPLIED, > + &ZVKNC_IMPLIED, > + &ZVKNG_IMPLIED, > + &ZVKNHB_IMPLIED, > + &ZVKS_IMPLIED, > + &ZVKSC_IMPLIED, > + &ZVKSG_IMPLIED, > + &SHA_IMPLIED, > + &SSCFG_IMPLIED, > + &SUPM_IMPLIED, > + &SSPM_IMPLIED, > + &SMCTR_IMPLIED, > + &SSCTR_IMPLIED, > + &SSSTATEEN_IMPLIED, > NULL > }; > > -- > 2.43.0 >