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[34.142.211.105]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df9142b00dsm45359075ad.49.2026.09.28.10.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 10:05:37 -0700 (PDT) Date: Mon, 28 Sep 2026 17:05:29 +0000 From: Pranjal Shrivastava To: Jason Gunthorpe Cc: Catalin Marinas , Jonathan Corbet , iommu@lists.linux.dev, "Joerg Roedel (AMD)" , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, Mark Rutland , Randy Dunlap , Robin Murphy , Shuah Khan , Will Deacon , David Matlack , Jean-Philippe Brucker , Jonathan Cameron , Nicolin Chen , Pasha Tatashin , patches@lists.linux.dev, Samiullah Khawaja , Mostafa Saleh , stable@vger.kernel.org, Vijayanand Jitta Subject: Re: [PATCH v7 7/9] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Message-ID: References: <0-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> <7-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com> On Mon, Sep 21, 2026 at 08:55:15PM -0300, Jason Gunthorpe wrote: > Each of these have their own unique situation, populate the tlbi right at > the top and pass it into arm_smmu_domain_inv_range(). They will diverge > further when the iommupt invalidation scheme is introduced. > > Reviewed-by: Nicolin Chen > Tested-by: Nicolin Chen > Signed-off-by: Jason Gunthorpe > --- > .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 21 ++++---- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 54 ++++++++++--------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 15 ++++-- > 3 files changed, 51 insertions(+), 39 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > index 2f76f649dcf1a5..faeec656da9e7f 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c > @@ -140,16 +140,19 @@ static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn, > { > struct arm_smmu_domain *smmu_domain = > container_of(mn, struct arm_smmu_domain, mmu_notifier); > - size_t size; > + struct arm_smmu_tlbi tlbi = { > + .tgsz_lg2 = smmu_domain->tgsz_lg2, > + .iova = start, > + /* > + * The mm_types defines vm_end as the first byte after the end > + * address, different from IOMMU subsystem using the last > + * address of an address range. > + */ > + .size = end - start, > + .iopte_size = PAGE_SIZE, > + }; > > - /* > - * The mm_types defines vm_end as the first byte after the end address, > - * different from IOMMU subsystem using the last address of an address > - * range. So do a simple translation here by calculating size correctly. > - */ > - size = end - start; > - > - arm_smmu_domain_inv_range(smmu_domain, start, size, PAGE_SIZE, false); > + arm_smmu_domain_tlbi(&tlbi, smmu_domain); > } > > static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index b7c9cd074924e4..4062ef2e13fe30 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2801,25 +2801,13 @@ static void arm_smmu_domain_tlbi_inv(struct arm_smmu_tlbi *tlbi, > } > } > > -void arm_smmu_domain_inv_range(struct arm_smmu_domain *smmu_domain, > - unsigned long iova, size_t size, > - unsigned int granule, bool leaf) > +void arm_smmu_domain_tlbi(struct arm_smmu_tlbi *tlbi, > + struct arm_smmu_domain *smmu_domain) A caller re-using the tlbi would overflow the 2-entry range.cmds[], since num_cmds is never reset or checked. Should we sanity check num_cmds here? Otherwise, Reviewed-by: Pranjal Shrivastava Thanks, Praan