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Tue, 29 Sep 2026 20:42:07 -0700 (PDT) Received: from sifive.com ([136.226.240.165]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2e2dd54c089sm3596195ad.50.2026.09.29.20.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 20:42:07 -0700 (PDT) Date: Wed, 30 Sep 2026 11:42:03 +0800 From: Max Chou To: Richard Henderson Cc: qemu-devel@nongnu.org, palmer@dabbelt.com, daniel.barboza@oss.qualcomm.com, Alistair.Francis@wdc.com, philmd@oss.qualcomm.com Subject: Re: [PATCH v3 00/11] tcg/riscv64: Fix AUIPC pair range validation Message-ID: References: <20260914000814.785155-1-richard.henderson@linaro.org> <983581aa-ffbd-40f9-8a9a-b6fbc066a1cf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <983581aa-ffbd-40f9-8a9a-b6fbc066a1cf@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:39::10; envelope-from=max.chou@sifive.com; helo=mail-pj2-x10.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2026-09-27 10:30, Richard Henderson wrote: > Ping. > > On 9/13/26 17:08, Richard Henderson wrote: > > Hi Max, > > > > In v2, the change from int32_t to uint32_t is pretty much > > the opposite of what should have been done, since all of > > these are logically signed values. I've adjusted all of > > the encoders to take signed inputs and assert in range. > > > > In the process, I noticed tha the branch range tests were > > off by one. Now all performed in exactly one place. > > > > Finally, tcg_out_ldst needed updates for AUIPC as well. > > > > I've tested this lightly so far; full testing on a rather > > slow riscv machine is still on-going. > > > > > > r~ > > Hi Richard, I’ve discovered a verification scenario that could trigger an unexpected segfault due to the AUIPC issue. The scenario involves running a debug cross-build (riscv64) of qemu-system-riscv64 with a plugin that instruments callback (e.g., libhotblocks.so) in a host riscv machine. (I used qemu-system-riscv64 with the same images here :p) Before applying this patchset, the internal qemu-system-riscv64 encountered an unexpected segfault during bootup. (P.S.: I built the riscv64 system mode image using buildroot qemu_riscv64_virt_defconfig.) Thanks, rnax