From: Thierry Reding <thierry.reding@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
Jessica Zhang <jesszhan0024@gmail.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Mikko Perttunen <mperttunen@nvidia.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v1 4/6] drm/tegra: Add support for 8-bit CPU interface
Date: Wed, 30 Sep 2026 10:48:19 +0200 [thread overview]
Message-ID: <arzMjoi2LcyfxCzN@orome> (raw)
In-Reply-To: <20260930070535.47130-5-clamor95@gmail.com>
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On Wed, Sep 30, 2026 at 10:05:33AM +0300, Svyatoslav Ryhel wrote:
> The display controller in Tegra20/30 SoCs features an 8-bit SPI interface
> that closely resembles the MIPI DBI Type B protocol and is referred to as
> '8-bit CPU'. Each display controller provides two such interfaces, which
> can be used to send MIPI DCS commands to initialize and control the panel
> while image data is transmitted via 16/18/24-line RGB.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> drivers/gpu/drm/tegra/Kconfig | 7 +
> drivers/gpu/drm/tegra/Makefile | 1 +
> drivers/gpu/drm/tegra/cpu-bridge.c | 427 +++++++++++++++++++++++++++++
> 3 files changed, 435 insertions(+)
> create mode 100644 drivers/gpu/drm/tegra/cpu-bridge.c
This doesn't need to be a separate driver. It should all live in dc.c.
Or maybe even rgb.c, since it uses pretty much the same pins and is
quite similar to it.
Thierry
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next prev parent reply other threads:[~2026-09-30 8:48 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 7:05 [PATCH v1 0/6] drm/tegra: Add support for Tegra20/Tegra30 8-bit CPU interface Svyatoslav Ryhel
2026-09-30 7:05 ` [PATCH v1 1/6] drm/tegra: dc: Expand available registers layouts Svyatoslav Ryhel
2026-09-30 7:15 ` sashiko-bot
2026-09-30 8:34 ` Thierry Reding
2026-09-30 8:55 ` Svyatoslav Ryhel
2026-09-30 7:05 ` [PATCH v1 2/6] drm/tegra: rgb: Parameterize configuration based on bus flags Svyatoslav Ryhel
2026-09-30 7:38 ` sashiko-bot
2026-09-30 7:05 ` [PATCH v1 3/6] dt-bindings: display: tegra: Document 8-bit CPU parallel interface Svyatoslav Ryhel
2026-09-30 7:15 ` sashiko-bot
2026-09-30 8:47 ` Thierry Reding
2026-09-30 9:00 ` Svyatoslav Ryhel
2026-09-30 10:34 ` Thierry Reding
2026-09-30 10:42 ` Svyatoslav Ryhel
2026-09-30 10:54 ` Thierry Reding
2026-09-30 11:10 ` Svyatoslav Ryhel
2026-09-30 11:41 ` Thierry Reding
2026-09-30 11:47 ` Svyatoslav Ryhel
2026-09-30 9:19 ` Mikko Perttunen
2026-09-30 9:52 ` Svyatoslav Ryhel
2026-09-30 10:50 ` Thierry Reding
2026-09-30 10:56 ` Svyatoslav Ryhel
2026-09-30 11:46 ` Thierry Reding
2026-09-30 11:56 ` Svyatoslav Ryhel
2026-09-30 12:58 ` Thierry Reding
2026-09-30 13:10 ` Svyatoslav Ryhel
2026-09-30 18:03 ` Svyatoslav Ryhel
2026-10-02 5:58 ` Mikko Perttunen
2026-09-30 11:51 ` Rob Herring (Arm)
2026-09-30 7:05 ` [PATCH v1 4/6] drm/tegra: Add support for 8-bit CPU interface Svyatoslav Ryhel
2026-09-30 7:25 ` sashiko-bot
2026-09-30 8:48 ` Thierry Reding [this message]
2026-09-30 9:02 ` Svyatoslav Ryhel
2026-09-30 10:39 ` Thierry Reding
2026-09-30 7:05 ` [PATCH v1 5/6] dt-bindings: display: panel: Document Hitachi TX10D07VM0BAA and LG LH400WV3 panels Svyatoslav Ryhel
2026-09-30 7:17 ` sashiko-bot
2026-09-30 7:05 ` [PATCH v1 6/6] drm/panel: Add Hitachi TX10D07VM0BAA and LG LH400WV3-SD04 MIPI DBI panel driver Svyatoslav Ryhel
2026-09-30 7:15 ` sashiko-bot
2026-09-30 9:02 ` Thierry Reding
2026-09-30 9:08 ` Svyatoslav Ryhel
2026-09-30 10:23 ` Thierry Reding
2026-09-30 10:34 ` Svyatoslav Ryhel
2026-09-30 10:43 ` Thierry Reding
2026-09-30 10:48 ` Svyatoslav Ryhel
2026-09-30 10:58 ` Thierry Reding
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