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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Bogdan Hamciuc , Ionut Vicovan , Andrew Lunn , Heiner Kallweit , Russell King , Clark Wang , Philipp Zabel , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Richard Cochran , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, imx@lists.linux.dev, linux-pci@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Vincent Guittot Subject: Re: [PATCH RFC v3 03/12] dt-bindings: PCI: nxp,s32g-pcie: Fix SerDes PHY phandle in example Message-ID: References: <20260919-s32g_serdes-v3-0-9d68868c1e89@oss.nxp.com> <20260919-s32g_serdes-v3-3-9d68868c1e89@oss.nxp.com> Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: CY8PR11CA0028.namprd11.prod.outlook.com (2603:10b6:930:4a::14) To GV2PR04MB11799.eurprd04.prod.outlook.com (2603:10a6:150:2cf::9) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB11799:EE_|DUZPR04MB9845:EE_ X-MS-Office365-Filtering-Correlation-Id: fbf40c06-1bcb-4bd7-61d3-08df29fc6c4b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|19092799006|23010399003|1800799024|376014|7416014|366016|6133799003|22082099003|10067099003|18002099003|3023799007|11063799006|4143699003|261009223027099003|56012099006; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org On Tue, Oct 13, 2026 at 04:37:21PM +0200, Jan Petrous wrote: > On Mon, Oct 12, 2026 at 01:43:05PM -0500, Frank Li wrote: > > On Sat, Sep 19, 2026 at 08:54:31AM +0200, Jan Petrous via B4 Relay wrote: > > > [You don't often get email from devnull+jan.petrous.oss.nxp.com@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > > > > > From: "Jan Petrous (OSS)" > > > > > > The example references the SerDes PHY as > > > > > > phys = <&serdes0 PHY_TYPE_PCIE 0 0>; > > > > > > i.e. the SerDes node itself with three PHY cells. That does not match > > > the SerDes binding: the per-lane child node is the generic PHY > > > provider and carries '#phy-cells = <0>', while the SerDes node itself > > > has no '#phy-cells' at all. > > > > > > Point the example at the PCIe lane child instead, which is also what > > > the S32G3 board device trees use. The dt-bindings/phy/phy.h include is > > > dropped along with the now-unused PHY_TYPE_PCIE constant. > > > > > > The schema itself is unchanged; 'phys: maxItems: 1' already describes > > > the corrected form. > > > > > > Signed-off-by: Jan Petrous (OSS) > > > --- > > > Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml | 3 +-- > > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml > > > index 66a050028278..29323e50bd8b 100644 > > > --- a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml > > > +++ b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml > > > @@ -82,7 +82,6 @@ unevaluatedProperties: false > > > examples: > > > - | > > > #include > > > - #include > > > > > > bus { > > > #address-cells = <2>; > > > @@ -124,7 +123,7 @@ examples: > > > ranges; > > > > > > device_type = "pci"; > > > - phys = <&serdes0 PHY_TYPE_PCIE 0 0>; > > > + phys = <&serdes0_pcie0>; > > > > I don't think it fix somethings. The "serdes0" just a label, point to > > provider, which is not neccsary that "#phy-cells" is 0. > > > > Examples just show need how many phys and don't care about phy provider's > > arguments > > > > The example validates either way, agreed. The three cells are the > '#phy-cells = <3>' of the downstream nxp,s32cc-serdes binding, which > was never posted upstream; patch 1 is the only SerDes binding for S32G > and has no three-cell provider. I would rather have the example match > it. > > The form depends on the outcome of your patch 1 comment, so I will > keep this patch in sync with that. If you prefer the phys line > untouched, I can drop it and keep only the ranges fix v4 adds here. This patch is not important. suggest drop it. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Geert Uytterhoeven , Magnus Damm , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Bogdan Hamciuc , Ionut Vicovan , Andrew Lunn , Heiner Kallweit , Russell King , Clark Wang , Philipp Zabel , Maxime Chevallier , Maxime Coquelin , Alexandre Torgue , Chester Lin , Matthias Brugger , Ghennadi Procopciuc , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Richard Cochran , linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, imx@lists.linux.dev, linux-pci@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Vincent Guittot Subject: Re: [PATCH RFC v3 03/12] dt-bindings: PCI: nxp,s32g-pcie: Fix SerDes PHY phandle in example Message-ID: References: <20260919-s32g_serdes-v3-0-9d68868c1e89@oss.nxp.com> <20260919-s32g_serdes-v3-3-9d68868c1e89@oss.nxp.com> Content-Type: text/plain; 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Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > > > > > From: "Jan Petrous (OSS)" > > > > > > The example references the SerDes PHY as > > > > > > phys = <&serdes0 PHY_TYPE_PCIE 0 0>; > > > > > > i.e. the SerDes node itself with three PHY cells. That does not match > > > the SerDes binding: the per-lane child node is the generic PHY > > > provider and carries '#phy-cells = <0>', while the SerDes node itself > > > has no '#phy-cells' at all. > > > > > > Point the example at the PCIe lane child instead, which is also what > > > the S32G3 board device trees use. The dt-bindings/phy/phy.h include is > > > dropped along with the now-unused PHY_TYPE_PCIE constant. > > > > > > The schema itself is unchanged; 'phys: maxItems: 1' already describes > > > the corrected form. > > > > > > Signed-off-by: Jan Petrous (OSS) > > > --- > > > Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml | 3 +-- > > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml > > > index 66a050028278..29323e50bd8b 100644 > > > --- a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml > > > +++ b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml > > > @@ -82,7 +82,6 @@ unevaluatedProperties: false > > > examples: > > > - | > > > #include > > > - #include > > > > > > bus { > > > #address-cells = <2>; > > > @@ -124,7 +123,7 @@ examples: > > > ranges; > > > > > > device_type = "pci"; > > > - phys = <&serdes0 PHY_TYPE_PCIE 0 0>; > > > + phys = <&serdes0_pcie0>; > > > > I don't think it fix somethings. The "serdes0" just a label, point to > > provider, which is not neccsary that "#phy-cells" is 0. > > > > Examples just show need how many phys and don't care about phy provider's > > arguments > > > > The example validates either way, agreed. The three cells are the > '#phy-cells = <3>' of the downstream nxp,s32cc-serdes binding, which > was never posted upstream; patch 1 is the only SerDes binding for S32G > and has no three-cell provider. I would rather have the example match > it. > > The form depends on the outcome of your patch 1 comment, so I will > keep this patch in sync with that. If you prefer the phys line > untouched, I can drop it and keep only the ranges fix v4 adds here. This patch is not important. suggest drop it. Frank > > BR. > /Jan >