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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Cc: <intel-xe@lists.freedesktop.org>, <matthew.brost@intel.com>,
	<anshuman.gupta@intel.com>, <badal.nilawar@intel.com>,
	<vinay.belgaumkar@intel.com>, <riana.tauro@intel.com>,
	<karthik.poosa@intel.com>, <sk.anirban@intel.com>,
	<raag.jadav@intel.com>, <michal.wajdeczko@intel.com>,
	<aravind.iddamsetty@linux.intel.com>,
	<umesh.nerlige.ramappa@intel.com>,
	<dnyaneshwar.bhadane@intel.com>, <anoop.c.vijay@intel.com>
Subject: Re: [PATCH v9 06/10] drm/xe/sysctrl: Fix mailbox header handling
Date: Mon, 12 Oct 2026 20:28:02 -0400	[thread overview]
Message-ID: <as17EpmqkfoSG0-b@intel.com> (raw)
In-Reply-To: <20260924060900.146167-18-mallesh.koujalagi@intel.com>

On Thu, Sep 24, 2026 at 11:39:07AM +0530, Mallesh Koujalagi wrote:
> The mailbox header was defined as __le32, which required
> cpu_to_le32() and le32_to_cpu() conversions whenever it was
> write or read.
> 
> These conversions are unnecessary because the header is always
> handled as a 32-bit value, not as raw bytes. It is written with
> xe_mmio_write32() and read with xe_mmio_read32(), which already
> handle any required byte-order conversion through the underlying
> writel()/readl() accessors.
> 
> As a result, the header value is already in CPU byte order when
> used by the driver. Keeping the extra conversions had no effect
> on little-endian systems and could cause an incorrect on
> big-endian systems.
> 
> So use u32 for the mailbox header and remove the unnecessary
> endianness conversions.
> 
> Fixes: 1f95f618182b ("drm/xe/xe_sysctrl: Add System Controller mailbox communication support")
> Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> Tested-by: Anoop Vijay <anoop.c.vijay@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
> v9:
> - Update commit message. (Michal)
> - Use fix tag. (Umesh)
> - drop __packed.
> - s/simplify/Fix/
> ---
>  drivers/gpu/drm/xe/xe_sysctrl_mailbox.c | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
> index 2fb317175922..2e4247914bf9 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
> @@ -20,20 +20,20 @@
>  #include "xe_sysctrl_mailbox_types.h"
>  
>  struct xe_sysctrl_mailbox_msg_hdr {
> -	__le32 data;
> -} __packed;
> +	u32 data;
> +};
>  
>  #define XE_SYSCTRL_HDR_GROUP_ID(hdr) \
> -	FIELD_GET(SYSCTRL_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
> +	FIELD_GET(SYSCTRL_HDR_GROUP_ID_MASK, (hdr)->data)
>  
>  #define XE_SYSCTRL_HDR_COMMAND(hdr) \
> -	FIELD_GET(SYSCTRL_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
> +	FIELD_GET(SYSCTRL_HDR_COMMAND_MASK, (hdr)->data)
>  
>  #define XE_SYSCTRL_HDR_IS_RESPONSE(hdr) \
> -	FIELD_GET(SYSCTRL_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
> +	FIELD_GET(SYSCTRL_HDR_IS_RESPONSE, (hdr)->data)
>  
>  #define XE_SYSCTRL_HDR_RESULT(hdr) \
> -	FIELD_GET(SYSCTRL_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
> +	FIELD_GET(SYSCTRL_HDR_RESULT_MASK, (hdr)->data)
>  
>  static int sysctrl_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask,
>  				  unsigned int timeout_ms)
> @@ -112,8 +112,8 @@ static int sysctrl_prepare_command(struct xe_device *xe,
>  		return -ENOMEM;
>  
>  	hdr = (struct xe_sysctrl_mailbox_msg_hdr *)buffer;
> -	hdr->data = cpu_to_le32(FIELD_PREP(SYSCTRL_HDR_GROUP_ID_MASK, group_id) |
> -				     FIELD_PREP(SYSCTRL_HDR_COMMAND_MASK, command));
> +	hdr->data = FIELD_PREP(SYSCTRL_HDR_GROUP_ID_MASK, group_id) |
> +		    FIELD_PREP(SYSCTRL_HDR_COMMAND_MASK, command);
>  
>  	if (data_in && data_in_len)
>  		memcpy(buffer + sizeof(*hdr), data_in, data_in_len);
> -- 
> 2.48.1
> 

  parent reply	other threads:[~2026-10-13  0:28 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-24  6:09 [PATCH v9 00/10] drm/xe/sysctrl: Clean up error handling in Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 01/10] drm/xe/sysctrl: Return error codes from sysctrl_wait_bit_clear() Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 02/10] drm/xe/sysctrl: Return error codes from sysctrl_wait_bit_set() Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 03/10] drm/xe/sysctrl: Make sysctrl_write_frame() void Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 04/10] drm/xe/sysctrl: Make sysctrl_read_frame() void Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 05/10] drm/xe/sysctrl: Use xe_assert() for payload size validation Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 06/10] drm/xe/sysctrl: Fix mailbox header handling Mallesh Koujalagi
2026-09-24 14:10   ` Umesh Nerlige Ramappa
2026-10-13  0:28   ` Rodrigo Vivi [this message]
2026-09-24  6:09 ` [PATCH v9 07/10] drm/xe/sysctrl: Replace FIELD_GET() with REG_FIELD_GET() Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 08/10] drm/xe/sysctrl: Improve firmware response error logging Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 09/10] drm/xe/sysctrl: Log group and command ID on mailbox failure Mallesh Koujalagi
2026-09-24  6:09 ` [PATCH v9 10/10] drm/xe/sysctrl: Report 'System Controller event' error using SIGID Mallesh Koujalagi
2026-09-24  6:50 ` ✓ CI.KUnit: success for drm/xe/sysctrl: Clean up error handling in (rev7) Patchwork
2026-09-24  7:27 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-24 20:31 ` ✗ Xe.CI.FULL: failure " Patchwork

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