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"PL1" : "PL2") > > -/* Index of memory controller in READ_THERMAL_DATA output */ > +/* Sensor byte indices in READ_THERMAL_DATA output for BMG. */ > #define TEMP_INDEX_MCTRL 2 > +#define TEMP_INDEX_PCIE 10 > +#define BMG_G21_TEMP_INDEX_PCIE 8 > > -/* On CRI the memory controller temperatures are READ_THERMAL_DATA bytes 16..19. */ > +/* Sensor byte indices in READ_THERMAL_DATA output for CRI. */ > #define CRI_TEMP_INDEX_MCTRL 16 > #define CRI_TEMP_MCTRL_COUNT 4 > +#define CRI_TEMP_INDEX_PCIE 20 > > /* Mailbox sentinel reported for an unavailable temperature sensor */ > #define TEMP_MBX_INVALID 0xFF > @@ -1016,21 +1019,30 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val) > return 0; > } > > -static int get_pcie_temp(struct xe_hwmon *hwmon, long *val) > +static u8 xe_hwmon_pcie_temp_index(const struct xe_hwmon *hwmon) > +{ > + if (hwmon->xe->info.platform == XE_CRESCENTISLAND) > + return CRI_TEMP_INDEX_PCIE; > + > + if (hwmon->xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21) > + return BMG_G21_TEMP_INDEX_PCIE; > + > + return TEMP_INDEX_PCIE; > +} > + > +static int get_pcie_temp(const struct xe_hwmon *hwmon, long *val) > { > struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); > u32 data = 0; > int ret; > > ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, > - PCIE_SENSOR_GROUP_ID), &data, NULL); > + xe_hwmon_pcie_temp_index(hwmon) / sizeof(data)), > + &data, NULL); > if (ret) > return ret; > > - /* Sensor offset is different for G21 */ > - if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21) > - data = REG_FIELD_GET(PCIE_SENSOR_MASK, data); > - > + data >>= (xe_hwmon_pcie_temp_index(hwmon) % sizeof(data)) * BITS_PER_BYTE; > data = REG_FIELD_GET(TEMP_MASK, data); > if (!mbx_temp_valid(hwmon, data)) { > drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n"); > diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h > index 94575c476e3d..00c4fc7d0124 100644 > --- a/drivers/gpu/drm/xe/xe_pcode_api.h > +++ b/drivers/gpu/drm/xe/xe_pcode_api.h > @@ -58,8 +58,6 @@ > #define READ_THERMAL_LIMITS 0x0 > #define READ_THERMAL_CONFIG 0x1 > #define READ_THERMAL_DATA 0x2 > -#define PCIE_SENSOR_GROUP_ID 0x2 > -#define PCIE_SENSOR_MASK REG_GENMASK(31, 16) > > #define PCODE_LATE_BINDING 0x5C > #define GET_CAPABILITY_STATUS 0x0 > -- > 2.25.1 >