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Wed, 14 Oct 2026 03:56:51 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 69E3ulRS31851140 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 14 Oct 2026 03:56:47 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6E7732004B; Wed, 14 Oct 2026 03:56:47 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D9DC22004D; Wed, 14 Oct 2026 03:56:44 +0000 (GMT) Received: from linux.ibm.com (unknown [9.126.150.29]) by smtpav03.fra02v.mail.ibm.com (Postfix) with SMTP; Wed, 14 Oct 2026 03:56:44 +0000 (GMT) Date: Wed, 14 Oct 2026 09:26:43 +0530 From: Srikar Dronamraju To: Shrikanth Hegde Cc: Tim Chen , christophe.leroy@csgroup.eu, linux-kernel@vger.kernel.org, ritesh.list@gmail.com, kprateek.nayak@amd.com, yu.c.chen@intel.com, vineethr@linux.ibm.com, vincent.guittot@linaro.org, npiggin@gmail.com, mpe@ellerman.id.au, maddy@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, peterz@infradead.org Subject: Re: [PATCH 0/4] powerpc/topology: Introduce llc_override debugfs Message-ID: Reply-To: Srikar Dronamraju References: <20261012102037.2477378-1-sshegde@linux.ibm.com> <0cbd60fcf328ffcb317739f60d327da3af6145f1.camel@linux.intel.com> <4d0f2f4631f2f836bb1aec140c2c8e3e11d7ba20.camel@linux.intel.com> <5f107344-7ddf-402e-809c-7229ff6fb6d5@linux.ibm.com> X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <5f107344-7ddf-402e-809c-7229ff6fb6d5@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE0MDAxNCBTYWx0ZWRfX5/BcnfZQgv0l ml3C+7XXI5kaph27yFTd4zzUTYlRErKeRauJFVd2TEaUcNKYYYSS6b+1Bmg+nzzxJm+w/9jZOIf gu4jNmqW2TVRAGCJ4DFjsRstiR7URA0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE0MDAxNCBTYWx0ZWRfX4/yatxwiFPxO NUaM9Hd4WxgnVBMIs7soHVA4rVbG9JxyYD4rbL0VCNI8F/dObhYeXQ11BWFZp132HIuPipsTO/k R30yGKCH1nJIcAJ3Ojfo+RJ88vzr5pjCh1pyK6ZDSOJnhjd6yfJ91jWrcTaIgoF7i7fs6coGChU aC+3jUazSMVt8OKghRcSRq1cHLxXv3rZr+uW57wqLwJ8YSgh5Scag1nhWKRL91qZBjUvXzzEkzO HlgegW9WWMBOmdcX+yv2iigxJgx8v1oNsVqNBXS1zs+pevKoMzH/bojs9k05V7YebVeb3MhBuzp NyUuNGHW7cBmoHBFnO7uyrvovCF5I8Byo3QEhBxTUu92hqP4HSpO2NkzuP254ijVIr1mWrzvbSc tkZ6k0WbWymQ6vfqrMfIFD1qLXP25GkIm1rYkxwLtSum1SSE7S/Y+ICwcZReM0uDFxA2Y9G3vAQ To73ZpwFXSU1v2OakuA== X-Proofpoint-GUID: Asy4W-E04gs761vcQhbCV1L4xL7cEaqm X-Authority-Analysis: v=2.4 cv=RoFQvymK c=1 sm=1 tr=0 ts=6acefd85 cx=c_pps a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17 a=8nJEP1OIZ-IA:10 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=Uhm1o-73ascBbd6UxXcA:9 a=wPNLvfGTeEIA:10 X-Proofpoint-ORIG-GUID: xE-0b0eWmCyVk7Z1RUkQVKXJV0TyXqkj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610140014 * Shrikanth Hegde [2026-10-14 08:46:11]: > On 10/14/26 2:14 AM, Tim Chen wrote: > > On Tue, 2026-10-13 at 15:28 +0530, Shrikanth Hegde wrote: > > > > > > > - SMT: patch 3 adds SD_SHARE_LLC only to MC/PKG, so for "smt" the > > flags are as before. I think it is possible for P9 to have > > shared_caches between two cores: > > > > /* > > * P9 has a slightly odd architecture where pairs of cores share an L2 cache. > > * This topology makes it *much* cheaper to migrate tasks between adjacent cores > > * since the migrated task remains cache hot. We want to take advantage of this > > * at the scheduler level so an extra topology level is required. > > */ > > > > the CACHE level also has SD_SHARE_LLC, and highest_flag_domain() picks it, so sd_llc spans > > cpu_l2_cache_map. shared_caches is only set when that map is wider > > than the core's threads, e.g. a P9 core pair sharing an L2: > > > > CPU: 0 1 2 3 | 4 5 6 7 > > cpu_smt_mask(): core A | core B > > sd_llc (CACHE): 0-7 > > > > The ids follow cpu_smt_mask(), so 0-3 and 4-7 get different ids > > while sd_llc and sd_llc_size cover all eight, and > > cpus_share_cache(0, 4) is false, which is incorrect. > > > > Yes. I doubt anyone wants to try this experiment on Power9. > But yes, functionally updating the flags is needed. > > @srikar, > That is also the reason for having the disabled. By default on P9, > llc will be at CACHE domain. But, one may want to experiment with =smt > which i doubt anyone will ever do. > I think P9 is a very valid point, but I don't think we should look at disable as an option just for this. I would say, lets keep it simple now, just have an option rather a toggle to have LLC as MC/PKG for experimentation purpose. Switch the toggle and it does back to regular LLC mode. Also we don't know how the future Power Systems LLCs will look like. So keeping it a simple toggle, will reduce pain and increase our flexibility for the future. Whether the toggle will switch to MC or PKG could be decided based on the experiment results. -- Thanks and Regards Srikar Dronamraju