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Tue, 13 Oct 2026 20:06:38 -0700 (PDT) Date: Wed, 14 Oct 2026 11:06:09 +0800 From: Inochi Amaoto To: Chen Wang , nick@detello.com, sophgo@lists.linux.dev, Inochi Amaoto Cc: inochiama@outlook.com Subject: Re: SG2000 display: DSI host + LT8912B HDMI working on v7.2, intent to upstream Message-ID: References: <817ee00d07821f32f11fa0fdf961540c@detello.com> Precedence: bulk X-Mailing-List: sophgo@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Oct 14, 2026 at 10:43:12AM +0800, Chen Wang wrote: > Adding inochi's gmail address, which is the email address he currently uses. > > Inochi, could you please help reply Nick on this? > > Thanks, > > Chen > > On 10/13/2026 8:49 PM, nick@detello.com wrote: > > (Resent in plain text; the list rejected the HTML copy.) > > > > On 2026-10-13 02:24, nick@detello.com wrote: > > > Hi Chen, Inochi, > > > > > > I have the SG2000 display path working on v7.2 with two small kernel > > > patches: DISP, DSI MAC and D-PHY driven by a new DRM host driver, > > > through the in-tree lontium-lt8912b bridge, to HDMI at 1280x720@60 > > > over > > > two lanes. It's tested on both cores (RISC-V and ARM) on the Nix Badge > > > 2.0, > > > a custom board around the Milk-V Duo S module: console on HDMI and a > > > 15 fps framebuffer animation. > > > > > > Two questions before I prepare the submission: > > > > > > 1. Is either of you, or anyone you know of, working on the VO/DSI > > > block > > >    for cv18xx/SG2000? I would rather join than duplicate. IIRC, there is no other ones, maybe someone has done similar, but they are not opened and I am not sure why. I already had a plan and finished bindings, but I am in bad health so I have limit time on it (and this is why I may have a bad respond time in LKML). The driver is a hard thing as I need to cover some SoCs with simliar design. > > > 2. Any preference on where the host driver lives > > >    (drivers/gpu/drm/sophgo/?) and on compatibles before I write the > > >    bindings? The branch uses sophgo,sg2000-dsi and a > > >    sophgo,sg2000-vip-sys syscon, and adds one clock ID > > >    (CLK_DSI_SYNTH_SRC) to the cv1800 binding header. > > > > > > Code, as one reviewable PR against the board's NixOS repo: > > >   https://github.com/NixVegas/BadgeOS/pull/8 > > >   Driver:  pkgs/video/sophgo-dsi/src/sophgo-dsi.c (~1,500 lines, > > >            register provenance from sophgo/osdrv cited in place) > > >   Patches: pkgs/kernel/patches/ (clk-cv18xx: poll DISPPLL's real lock > > >            bit and expose the DSI source gate; lt8912b: do the bridge > > >            setup in pre_enable, between the host's LP-11 and HS) > > >   DT:      pkgs/firmware/dts/sg2000-milkv-duo-s-common.dtsi > > > I have checked the PR and find it is very simple. I do not think it reflect the real hardware, IIRC it will be divided into several parts with phy/dsi/vpu/isp/pinctrl/clk. And your driver only contains some of them. If you take these thing with a whole view, you will see they are things that work together. I also disagree with the clk data fix. Although it should expose a new div2 clock, the default configuration of DISP PLL should not be changed, but If I did make a mistake, please send this patch directly and I am happy with that. ^^. Sorry for no detailed information, The detailed datasheet is not opened, they are only opened to the trusted one, So I can not share you with the detailed design and how the device is co-worked. But at least I can told you, you may need pinctrl and clock-frequency properties to all display node. Regards, Inochi > > > Planned order: the clk fix; display nodes for sg2000.dtsi and for the > > > Duo S DTS Joshua Milas's series added in July; the DSI host as an RFC > > > to dri-devel; then the lt8912b change, which as written is specific to > > > this host (fixed HDMI mode, LVDS and PM paths dropped) and will be > > > rebased on Maxime's atomic-callback conversion on drm-misc-next before > > > it goes anywhere. Known gaps before the RFC: fixed mode (no EDID, no > > > hot-plug; HPD goes to the bridge on this board), no vblank interrupt, > > > and register sequences reproduced from the vendor driver rather than > > > modelled. > > > > > > Happy to share a video, serial logs or register traces. The driver was > > > developed with Claude Code assistance; I have read and tested every > > > line and will carry the review. > > > > > > Thanks, > > > Nick DeTello