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From: Niklas Cassel <cassel@kernel.org>
To: Xincheng Zhang <zhangxincheng@ultrarisc.com>
Cc: "Jingoo Han" <jingoohan1@gmail.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Jia Wang" <wangjia@ultrarisc.com>,
	"Frank Li" <Frank.Li@kernel.org>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] PCI: dwc: Allow drivers to skip MEM outbound iATU setup
Date: Wed, 14 Oct 2026 10:27:57 +0200	[thread overview]
Message-ID: <as89A9X9wAHJ-dIR@ryzen> (raw)
In-Reply-To: <20260905025635.211390-2-zhangxincheng@ultrarisc.com>

On Sat, Sep 05, 2026 at 10:56:34AM +0800, Xincheng Zhang wrote:
> Some DWC-based controllers do not require outbound iATU windows for MEM
> transactions. For those platforms, programming outbound iATU windows for
> host bridge MEM ranges is unnecessary and may constrain the available MEM
> aperture.
> 
> The DWC PCIe RP Controller Databook v6.00a, section 3.12.2, describes the
> default outbound no-match behavior as pass-through. Section 3.12.5.6, "No
> Address Match Result", says the address is not translated and programmable
> TLP header fields come from the application transmit interface.
> 
> This no-match path cannot translate between different parent-bus and PCI
> addresses, so require skipped MEM ranges to be identity-mapped.
> 
> Add dw_pcie_rp::bypass_ob_mem_iatu so drivers can skip generic MEM iATU
> setup while using the common DWC host init path.
> 
> Existing drivers keep the current behavior because the flag defaults to
> false. The I/O iATU setup does not use the MEM resource iterator, and the
> iterator may be uninitialized when MEM setup is skipped. Avoid using it in
> the I/O iATU error path.
> 
> Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com>
> ---
>  .../pci/controller/dwc/pcie-designware-host.c   | 17 +++++++++++++++--
>  drivers/pci/controller/dwc/pcie-designware.h    |  1 +
>  2 files changed, 16 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f5a38e6fd8d79..b06797b4e31d2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -918,6 +918,20 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  		atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset;
>  		atu.pci_addr = entry->res->start - entry->offset;
>  
> +		if (pp->bypass_ob_mem_iatu) {

Sorry for commenting on this patch after it was accepted.

But... since this behavior is intrinsic to the DWC controller, rather than
being SoC specific... Why bother creating a flag for it?

Is there a reason why this can't just be a simple:

if (atu.parent_bus_addr == atu.pci_addr)
	continue;

?


Kind regards,
Niklas

  parent reply	other threads:[~2026-10-14  8:28 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-05  2:56 [PATCH v2 0/2] PCI: dwc: Support large BARs on UltraRISC DP1000 Xincheng Zhang
2026-09-05  2:56 ` [PATCH v2 1/2] PCI: dwc: Allow drivers to skip MEM outbound iATU setup Xincheng Zhang
2026-09-05  3:04   ` sashiko-bot
2026-10-14  8:27   ` Niklas Cassel [this message]
2026-09-05  2:56 ` [PATCH v2 2/2] PCI: ultrarisc: Skip MEM outbound iATU setup on DP1000 Xincheng Zhang
2026-09-05  3:10   ` sashiko-bot
2026-10-14  6:03 ` [PATCH v2 0/2] PCI: dwc: Support large BARs on UltraRISC DP1000 Manivannan Sadhasivam

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