Re: [PATCH v10 03/13] iommu/arm-smmu-v3: Add ARM_SMMU_FEAT_EVTQ for the event queue

[Nicolin Chen <nicolinc@nvidia.com>]

On Sun, Oct 04, 2026 at 01:20:52PM -0700, Nicolin Chen wrote:
> Sashiko is only right about the small waste of the MSI vector since
> it's unused. But, that nvec decrement trick only works for PRIQ, as
> its MSI index is at top of the list:
> 
>    enum arm_smmu_msi_index {
> 	EVTQ_MSI_INDEX,
> 	GERROR_MSI_INDEX,
> 	PRIQ_MSI_INDEX,
> 	ARM_SMMU_MAX_MSIS, // "nvec--" shifts up this, skipping PRIQ
>    };
> 
> On the other hand, EVTQ_MSI_INDEX is at 0. Skipping it would need to
> shift the entire index list; struct arm_smmu_msi_cfg would not work
> straightforwardly as today.

I made a small change swapping those two indexes. Though it cannot
break the dependency on the vectors, I think we should be fine as
there should be no use case for !FEAT_EVTQ && FEAT_PRI.

-----------------------prep patch--------------------------
@@ -59,4 +59,4 @@ static DEFINE_STATIC_KEY_FALSE(arm_smmu_erratum_repeat_tlbi_cfgi_key);
 enum arm_smmu_msi_index {
-	EVTQ_MSI_INDEX,
 	GERROR_MSI_INDEX,
+	EVTQ_MSI_INDEX,
 	PRIQ_MSI_INDEX,
@@ -70,7 +70,2 @@ static_assert(sizeof(struct arm_smmu_cd) == NUM_ENTRY_QWORDS * sizeof(u64));
 static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
-	[EVTQ_MSI_INDEX] = {
-		ARM_SMMU_EVTQ_IRQ_CFG0,
-		ARM_SMMU_EVTQ_IRQ_CFG1,
-		ARM_SMMU_EVTQ_IRQ_CFG2,
-	},
 	[GERROR_MSI_INDEX] = {
@@ -80,2 +75,7 @@ static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = {
 	},
+	[EVTQ_MSI_INDEX] = {
+		ARM_SMMU_EVTQ_IRQ_CFG0,
+		ARM_SMMU_EVTQ_IRQ_CFG1,
+		ARM_SMMU_EVTQ_IRQ_CFG2,
+	},
 	[PRIQ_MSI_INDEX] = {
@@ -4967,3 +4967,3 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
 
-	/* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */
+	/* Allocate MSIs for gerror, evtq and priq. Ignore cmdq */
 	ret = platform_device_msi_init_and_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg);
@@ -4974,4 +4974,4 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
 
-	smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX);
 	smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX);
+	smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX);
 	smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX);
-----------------------------------------------------------

-----------------------nvec patch--------------------------
@@ -4952,3 +4961,11 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu)
 	writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0);
-	writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);
+
+	/* PRIQ's vector needs EVTQ's to be kept */
+	WARN_ON_ONCE(!(smmu->features & ARM_SMMU_FEAT_EVTQ) &&
+		     (smmu->features & ARM_SMMU_FEAT_PRI));
+
+	if (smmu->features & ARM_SMMU_FEAT_EVTQ)
+		writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0);
+	else
+		nvec--;
 
-----------------------------------------------------------

I also did a rebase on arm/smmu/updates, resolving merge conflict.

I can quickly respin a v11 once we finalize the discussions in the
other thread. 

Thanks
Nicolin