All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jisheng Zhang <jszhang@kernel.org>
To: kernel test robot <lkp@intel.com>
Cc: oe-kbuild-all@lists.linux.dev, Paul Walmsley <pjw@kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [pjw-riscv:temp-testing 22/25] arch/riscv/kernel/cpufeature.c:943:7: error: '_pgtable_l4_enabled' undeclared; did you mean 'pgtable_l4_enabled'?
Date: Thu, 8 Oct 2026 21:50:56 +0800	[thread overview]
Message-ID: <asefwIv5ek2mFPdX@xhacker> (raw)
In-Reply-To: <202610072042.NzBrZDn5-lkp@intel.com>

On Wed, Oct 07, 2026 at 08:52:03PM +0200, kernel test robot wrote:
> tree:   https://git.kernel.org/pub/scm/linux/kernel/git/pjw/riscv.git temp-testing
> head:   2bb0a02401f8949ca3f8c12cf1b6cf01bf41eb9e
> commit: 016fdf4cebe05b68f13128f1eb12537b10a89d66 [22/25] riscv: support early isa ext and use it to optimize pgtable_l4|l5_enabled
> config: riscv-randconfig-2000-20261007 (https://download.01.org/0day-ci/archive/20261007/202610072042.NzBrZDn5-lkp@intel.com/config)
> compiler: riscv32-linux-gcc (GCC) 8.5.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261007/202610072042.NzBrZDn5-lkp@intel.com/reproduce)

oops, I missed riscv32. Let me fix it and send out a new version.

> 
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes: https://lore.kernel.org/oe-kbuild-all/202610072042.NzBrZDn5-lkp@intel.com/
> 
> All errors (new ones prefixed by >>):
> 
>    arch/riscv/kernel/cpufeature.c: In function 'riscv_fill_hwcap_from_isa_string':
> >> arch/riscv/kernel/cpufeature.c:943:7: error: '_pgtable_l4_enabled' undeclared (first use in this function); did you mean 'pgtable_l4_enabled'?
>       if (_pgtable_l4_enabled)
>           ^~~~~~~~~~~~~~~~~~~
>           pgtable_l4_enabled
>    arch/riscv/kernel/cpufeature.c:943:7: note: each undeclared identifier is reported only once for each function it appears in
> >> arch/riscv/kernel/cpufeature.c:945:7: error: '_pgtable_l5_enabled' undeclared (first use in this function); did you mean 'pgtable_l5_enabled'?
>       if (_pgtable_l5_enabled)
>           ^~~~~~~~~~~~~~~~~~~
>           pgtable_l5_enabled
>    arch/riscv/kernel/cpufeature.c: In function 'riscv_fill_hwcap_from_ext_list':
>    arch/riscv/kernel/cpufeature.c:1108:7: error: '_pgtable_l4_enabled' undeclared (first use in this function); did you mean 'pgtable_l4_enabled'?
>       if (_pgtable_l4_enabled)
>           ^~~~~~~~~~~~~~~~~~~
>           pgtable_l4_enabled
>    arch/riscv/kernel/cpufeature.c:1110:7: error: '_pgtable_l5_enabled' undeclared (first use in this function); did you mean 'pgtable_l5_enabled'?
>       if (_pgtable_l5_enabled)
>           ^~~~~~~~~~~~~~~~~~~
>           pgtable_l5_enabled
> 
> 
> vim +943 arch/riscv/kernel/cpufeature.c
> 
>    882	
>    883	static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap)
>    884	{
>    885		struct device_node *node;
>    886		const char *isa;
>    887		int rc;
>    888		struct acpi_table_header *rhct;
>    889		acpi_status status;
>    890		unsigned int cpu;
>    891		u64 boot_vendorid;
>    892		u64 boot_archid;
>    893	
>    894		if (!acpi_disabled) {
>    895			status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
>    896			if (ACPI_FAILURE(status))
>    897				return;
>    898		}
>    899	
>    900		boot_vendorid = riscv_get_mvendorid();
>    901		boot_archid = riscv_get_marchid();
>    902	
>    903		for_each_possible_cpu(cpu) {
>    904			struct riscv_isainfo *isainfo = &hart_isa[cpu];
>    905			unsigned long this_hwcap = 0;
>    906			DECLARE_BITMAP(source_isa, RISCV_ISA_EXT_MAX) = { 0 };
>    907	
>    908			if (acpi_disabled) {
>    909				node = of_cpu_device_node_get(cpu);
>    910				if (!node) {
>    911					pr_warn("Unable to find cpu node\n");
>    912					continue;
>    913				}
>    914	
>    915				rc = of_property_read_string(node, "riscv,isa", &isa);
>    916				of_node_put(node);
>    917				if (rc) {
>    918					pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
>    919					continue;
>    920				}
>    921			} else {
>    922				rc = acpi_get_riscv_isa(rhct, cpu, &isa);
>    923				if (rc < 0) {
>    924					pr_warn("Unable to get ISA for the hart - %d\n", cpu);
>    925					continue;
>    926				}
>    927			}
>    928	
>    929			riscv_parse_isa_string(isa, source_isa);
>    930	
>    931			/*
>    932			 * These ones were as they were part of the base ISA when the
>    933			 * port & dt-bindings were upstreamed, and so can be set
>    934			 * unconditionally where `i` is in riscv,isa on DT systems.
>    935			 */
>    936			if (acpi_disabled) {
>    937				set_bit(RISCV_ISA_EXT_ZICSR, source_isa);
>    938				set_bit(RISCV_ISA_EXT_ZIFENCEI, source_isa);
>    939				set_bit(RISCV_ISA_EXT_ZICNTR, source_isa);
>    940				set_bit(RISCV_ISA_EXT_ZIHPM, source_isa);
>    941			}
>    942	
>  > 943			if (_pgtable_l4_enabled)
>    944				set_bit(RISCV_ISA_EXT_SV48, source_isa);
>  > 945			if (_pgtable_l5_enabled)
>    946				set_bit(RISCV_ISA_EXT_SV57, source_isa);
>    947	
>    948			/*
>    949			 * "V" in ISA strings is ambiguous in practice: it should mean
>    950			 * just the standard V-1.0 but vendors aren't well behaved.
>    951			 * Many vendors with T-Head CPU cores which implement the 0.7.1
>    952			 * version of the vector specification put "v" into their DTs.
>    953			 * CPU cores with the ratified spec will contain non-zero
>    954			 * marchid.
>    955			 */
>    956			if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0)
>    957				clear_bit(RISCV_ISA_EXT_V, source_isa);
>    958	
>    959			riscv_resolve_isa(source_isa, isainfo->isa, &this_hwcap, isa2hwcap);
>    960	
>    961			/*
>    962			 * All "okay" hart should have same isa. Set HWCAP based on
>    963			 * common capabilities of every "okay" hart, in case they don't
>    964			 * have.
>    965			 */
>    966			if (elf_hwcap)
>    967				elf_hwcap &= this_hwcap;
>    968			else
>    969				elf_hwcap = this_hwcap;
>    970	
>    971			if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
>    972				bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
>    973			else
>    974				bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
>    975		}
>    976	
>    977		if (!acpi_disabled && rhct)
>    978			acpi_put_table((struct acpi_table_header *)rhct);
>    979	}
>    980	
> 
> --
> 0-DAY CI Kernel Test Service
> https://github.com/intel/lkp-tests/wiki

      reply	other threads:[~2026-10-08 14:10 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-07 18:52 [pjw-riscv:temp-testing 22/25] arch/riscv/kernel/cpufeature.c:943:7: error: '_pgtable_l4_enabled' undeclared; did you mean 'pgtable_l4_enabled'? kernel test robot
2026-10-08 13:50 ` Jisheng Zhang [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=asefwIv5ek2mFPdX@xhacker \
    --to=jszhang@kernel.org \
    --cc=conor.dooley@microchip.com \
    --cc=lkp@intel.com \
    --cc=oe-kbuild-all@lists.linux.dev \
    --cc=pjw@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.