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Fri, 09 Oct 2026 02:18:36 -0700 (PDT) Received: from linaro.org ([2a10:d582:31e:0:fde2:547b:5069:256e]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a18bf135fasm39591195e9.5.2026.10.09.02.18.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Oct 2026 02:18:36 -0700 (PDT) Date: Fri, 9 Oct 2026 10:18:34 +0100 From: Jim MacArthur To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: Re: [PATCH] hw/intc/arm_gicv5: Make IRS_IDR0 reads return actual value, not 0 Message-ID: References: <20261008092327.4036856-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261008092327.4036856-1-peter.maydell@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Oct 08, 2026 at 10:23:27AM +0100, Peter Maydell wrote: > IN the code for handling reads of IRS_IDR0, we carefully construct > the correct value starting with cs->irs_idr0 and adjusting it. > However, we never actually write the final value into *data, so > the guest will always see zero. > > We didn't notice this before, because Linux happens to not care > about this register value except to check for the presence of > virtualization. > > Cc: qemu-stable@nongnu.org > Fixes: 405ad2e76f13254 ("hw/intc/arm_gicv5: Implement IRS ID regs") > Signed-off-by: Peter Maydell > --- > hw/intc/arm_gicv5.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c > index 08878193dfc..ebfb0878af3 100644 > --- a/hw/intc/arm_gicv5.c > +++ b/hw/intc/arm_gicv5.c > @@ -1433,6 +1433,7 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset, > /* ...which means VIRT_ONE_N is also RES0 */ > v &= ~R_IRS_IDR0_VIRT_ONE_N_MASK; > } > + *data = v; > return true; > > case A_IRS_IDR1: Reviewed-by: Jim MacArthur