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From: Chao Liu <chao.liu@processmission.com>
To: Mingliang Liu <liumingliang.dev@bytedance.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com,
	 Alistair.Francis@wdc.com, zhiwei_liu@linux.alibaba.com,
	liwei1518@gmail.com,  daniel.barboza@oss.qualcomm.com,
	richard.henderson@linaro.org
Subject: Re: [PATCH v4 2/3] disas/riscv: Support vabs.v pseudo-instruction
Date: Fri, 16 Oct 2026 00:10:41 +0800	[thread overview]
Message-ID: <atD680v20YjwUC1J@MacBook-Pro-4.local> (raw)
In-Reply-To: <20261015134337.3354723-3-liumingliang.dev@bytedance.com>

On Thu, Oct 15, 2026 at 09:43:36PM +0800, Mingliang Liu wrote:
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
> Signed-off-by: Mingliang Liu <liumingliang.dev@bytedance.com>
Tested-by: Chao Liu <chao.liu@processmission.com>

Thanks,
Chao
> ---
>  disas/riscv-op.c.inc | 3 ++-
>  disas/riscv.c        | 6 ++++++
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/disas/riscv-op.c.inc b/disas/riscv-op.c.inc
> index 07b56f5d52..425473ee61 100644
> --- a/disas/riscv-op.c.inc
> +++ b/disas/riscv-op.c.inc
> @@ -491,9 +491,10 @@ OP(vaadd_vx, "vaadd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
>  OP(vaaddu_vv, "vaaddu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vaaddu_vx, "vaaddu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
>  OP(vabd_vv, "vabd.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
> -OP(vabd_vx, "vabd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vabd_vx, "vabd.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm, rvcp_vabd_vx)
>  OP(vabdu_vv, "vabdu.vv", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vm)
>  OP(vabdu_vx, "vabdu.vx", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vm)
> +OP(vabs_v, "vabs.v", rv_codec_illegal, rv_fmt_vd_vs2_vm)
>  OP(vadc_vim, "vadc.vim", rv_codec_v_i, rv_fmt_vd_vs2_imm_vl)
>  OP(vadc_vvm, "vadc.vvm", rv_codec_v_r, rv_fmt_vd_vs2_vs1_vl)
>  OP(vadc_vxm, "vadc.vxm", rv_codec_v_r, rv_fmt_vd_vs2_rs1_vl)
> diff --git a/disas/riscv.c b/disas/riscv.c
> index b0102e47bc..e349f521e8 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -103,6 +103,7 @@ static const rvc_constraint rvcc_j[] = { rvc_rd_eq_x0, rvc_end };
>  static const rvc_constraint rvcc_ret[] = { rvc_rs1_eq_ra, rvc_end };
>  static const rvc_constraint rvcc_jr[] = { rvc_rd_eq_x0, rvc_imm_eq_zero,
>                                            rvc_end };
> +static const rvc_constraint rvcc_vabs_v[] = { rvc_rs1_eq_x0, rvc_end };
>  static const rvc_constraint rvcc_true[] = { rvc_end };
>  
>  /* pseudo-instruction metadata */
> @@ -242,6 +243,11 @@ static const rv_comp_data rvcp_fsgnjx_q[] = {
>      { },
>  };
>  
> +static const rv_comp_data rvcp_vabd_vx[] = {
> +    { &op_vabs_v, rvcc_vabs_v },
> +    { },
> +};
> +
>  /* Convert compressed insns into normal insns via pseudo expansion. */
>  #define DECOMP(X)  &(const rv_comp_data){ &X, rvcc_true }
>  
> -- 
> 2.39.5


  reply	other threads:[~2026-10-15 16:12 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-15 13:43 [PATCH v4 0/3] target/riscv: Add experimental Zvabd extension support Mingliang Liu
2026-10-15 13:43 ` [PATCH v4 1/3] target/riscv: Add support for the Zvabd extension Mingliang Liu
2026-10-15 15:53   ` Chao Liu
2026-10-15 13:43 ` [PATCH v4 2/3] disas/riscv: Support vabs.v pseudo-instruction Mingliang Liu
2026-10-15 16:10   ` Chao Liu [this message]
2026-10-15 13:43 ` [PATCH v4 3/3] tests/tcg/riscv64: Add Zvabd extension tests Mingliang Liu
2026-10-15 16:12   ` Chao Liu

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