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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48dfd4f8bb6sm566051f8f.34.2026.10.15.14.24.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2026 14:24:49 -0700 (PDT) Date: Thu, 15 Oct 2026 21:24:46 +0000 From: Mostafa Saleh To: sashiko-reviews@lists.linux.dev Cc: kvmarm@lists.linux.dev, Oliver Upton , Marc Zyngier Subject: Re: [PATCH v9 21/25] iommu/io-pgtable-arm: Support io-pgtable-arm in the hypervisor Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-22-smostafa@google.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, Oct 15, 2026 at 08:26:45PM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Low] arch: layering violation by including SMMUv3 header in generic io-pgtable-arm.h > -- > > commit 251567dd4618edfaa4984ef7282b71a0da331297 > Author: Mostafa Saleh > > iommu/io-pgtable-arm: Support io-pgtable-arm in the hypervisor > > To be able to populate the shadow stage-2 in the hypervisor, compile > io-pgtable-arm object for the hypervisor. This requires the hypervisor > to provide the iommu-pages allocator, redefine the address conversion > helpers, and stub out the DMA API. > > [ ... ] > > > diff --git a/drivers/iommu/io-pgtable-arm.h b/drivers/iommu/io-pgtable-arm.h > > index ba7cfdf7afa03..4278da41e406d 100644 > > --- a/drivers/iommu/io-pgtable-arm.h > > +++ b/drivers/iommu/io-pgtable-arm.h > > @@ -27,4 +27,13 @@ > > #define ARM_LPAE_TCR_PS_48_BIT 0x5ULL > > #define ARM_LPAE_TCR_PS_52_BIT 0x6ULL > > > > +#ifndef __KVM_NVHE_HYPERVISOR__ > > +#include "iommu-pages.h" > > +#define arm_lpae_alloc_data(obj) kmalloc_obj(obj) > > +#define arm_lpae_free_data(p) kfree(p) > > + > > +#else > > +#include "arm/arm-smmu-v3/pkvm/io-pgtable-arm-hyp.h" > > [Severity: Low] > Is this an intended architecture layering violation? The generic ARM LPAE page > table header drivers/iommu/io-pgtable-arm.h explicitly includes the > driver-specific header arm/arm-smmu-v3/pkvm/io-pgtable-arm-hyp.h when > compiled for the hypervisor. This tightly couples generic IOMMU framework code > directly to the SMMUv3 driver path. > > Should the hypervisor stubs be placed in a generic NVHE include directory > (e.g., arch/arm64/kvm/hyp/include/nvhe/) to maintain subsystem independence, > even if SMMUv3 is currently the only user? > No strong opinion, I think keeping it anywhere under drivers/iommu is fine. Thanks, Mostafa > > +#endif > > + > > #endif /* IO_PGTABLE_ARM_H_ */ > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20261015200903.2735565-1-smostafa@google.com?part=21