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Tue, 20 Oct 2026 12:02:09 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Tue, 20 Oct 2026 12:02:07 -0700 Date: Tue, 20 Oct 2026 12:02:05 -0700 From: Nicolin Chen To: Mostafa Saleh CC: , , , , , , , , , , , , , , , , , "Jason Gunthorpe" Subject: Re: [PATCH v9 03/25] iommu/arm-smmu-v3: Move IDR parsing to common functions Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-4-smostafa@google.com> X-Mailing-List: iommu@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261015200903.2735565-4-smostafa@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF00022BCA:EE_|CY5PR12MB6623:EE_ X-MS-Office365-Filtering-Correlation-Id: efc73460-af18-4fee-cbc2-08df2edcb2c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|82310400026|376014|1800799024|7416014|10067099003|18002099003|22082099003|4143699003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: //W+e18MRb3QY9C2Kj9fwIZG3lT8FrkiYXhRSkWHC+9ti54QcoraZGHWeWWx4MD8gE+ZJ0YV21BvuokqPYxLshNHsOMvD01TrcTcPuxq5XZh6GFBxZkJ9+9V2g80qzdnzBGD/zLhQ8yxAzQFHHOm4Yk7kFTEt0K/3CJXJGtp/4L6Er884mAhadHz+BO7leOSU3J5AEzdg+YENdWk3l4xDKHWSwvIHIeWlJGze7roHIyUGvyipAScwMjA+aAKk0akwNdwyx5Fe1JoUJ8KrC8ZtkrA/B7MfoO3wyzVCyj5yCbC1bZrcCnXQM5dR6Tc0YYqzmOphWDXhkMYR2/8dXba6gARRjTh4S6EhiNjQiSeza50s2+DKkIG8D7l8JYsDrTMe+DzzN2e1svpHeOEpt63gwt81zapf3eAH3m6wxGTFj3Akv/4bOkzU85CenquDlmz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Oct 2026 19:02:33.4742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: efc73460-af18-4fee-cbc2-08df2edcb2c1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF00022BCA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6623 On Thu, Oct 15, 2026 at 08:08:34PM +0000, Mostafa Saleh wrote: > The hypervisor SMMUv3 driver needs the same IDR0, IDR3, IDR5 and IIDR > parsing as the kernel driver, plus the IDR1 checks it depends on > (embedded implementation, ATTR_TYPES_OVR, StreamID size). Move them to > arm-smmu-v3-common-lib.c, which will be built for both, and the IIDR > implementer and product IDs to arm-smmu-v3.h. > > The two drivers use different device structs, so the shared code is > written against ARM_SMMU_OBJ, which each compilation unit defines. The > kernel maps it to struct arm_smmu_device. Static asserts check that the > fields the shared code uses exist with the expected types. > > The validity checks stay with the parsing. dev_err() and dev_info() > become arm_smmu_err() and arm_smmu_info(), defined per world next to > ARM_SMMU_OBJ, as the hypervisor cannot print to the console. The > disable_msipolling module parameter is passed as an argument so the > hypervisor can opt out, and cpus_have_cap() becomes > cpus_have_final_cap(), which the hypervisor can use. > > No functional change intended. > > Suggested-by: Jason Gunthorpe > Signed-off-by: Mostafa Saleh Reviewed-by: Nicolin Chen