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Allow > dma_bar to select an MW BAR and place the DMA ranges after that MW. > > DMA submaps have fixed BAR offsets, so a shared MW translation must > cover its configured size. Report that size as the translation alignment > and require it to be a power of two. > > Limit the host-visible MW size to exclude the DMA ranges. Older versions > of ntb_hw_epf treat the whole BAR as an MW. > > Signed-off-by: Koichiro Den > --- > Changes since v5: > - Include the host-side MW boundary handling and place this patch > after DMA discovery. > > drivers/ntb/hw/epf/ntb_hw_epf.c | 43 ++++- > drivers/pci/endpoint/functions/pci-epf-vntb.c | 147 +++++++++++++----- what's happen if miss match? host and endpoint may not run the same version kernel. ntb should be independ on endpoint part. So suggest split patch, so ntb can go though ntb subsystem. Frank > 2 files changed, 148 insertions(+), 42 deletions(-) > > diff --git a/drivers/ntb/hw/epf/ntb_hw_epf.c b/drivers/ntb/hw/epf/ntb_hw_epf.c > index e0016128b95c..975ea424de6a 100644 > --- a/drivers/ntb/hw/epf/ntb_hw_epf.c > +++ b/drivers/ntb/hw/epf/ntb_hw_epf.c > @@ -382,6 +382,23 @@ static int ntb_epf_mw_to_bar(struct ntb_epf_dev *ndev, int idx) > return ndev->barno_map[BAR_MW1 + idx]; > } > > +static resource_size_t ntb_epf_mw_offset(struct ntb_epf_dev *ndev, int idx) > +{ > + return !idx ? readl(ndev->ctrl_reg + NTB_EPF_CTRL(mw1_offset)) : 0; > +} > + > +static resource_size_t ntb_epf_mw_size(struct ntb_epf_dev *ndev, int bar) > +{ > + resource_size_t end; > + > + end = pci_resource_len(ndev->ntb.pdev, bar); > + /* The DMA submap offset marks the end of an MW sharing this BAR. */ > + if (ndev->dma.submap.size && ndev->dma.submap.bar == bar) > + end = min(end, ndev->dma.submap.offset); > + > + return end; > +} > + > static int ntb_epf_mw_count(struct ntb_dev *ntb, int pidx) > { > struct ntb_epf_dev *ndev = ntb_ndev(ntb); > @@ -420,7 +437,7 @@ static int ntb_epf_mw_get_align(struct ntb_dev *ntb, int pidx, int idx, > *size_align = 1; > > if (size_max) > - *size_max = pci_resource_len(ndev->ntb.pdev, bar); > + *size_max = ntb_epf_mw_size(ndev, bar); > > return 0; > } > @@ -707,7 +724,7 @@ static int ntb_epf_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, > if (bar < 0) > return bar; > > - mw_size = pci_resource_len(ntb->pdev, bar); > + mw_size = ntb_epf_mw_size(ndev, bar); > > if (size > mw_size) { > dev_err(dev, "Size:%pa is greater than the MW size %pa\n", > @@ -739,21 +756,20 @@ static int ntb_epf_peer_mw_get_addr(struct ntb_dev *ntb, int idx, > phys_addr_t *base, resource_size_t *size) > { > struct ntb_epf_dev *ndev = ntb_ndev(ntb); > - u32 offset = 0; > + resource_size_t offset; > int bar; > > - if (idx == 0) > - offset = readl(ndev->ctrl_reg + NTB_EPF_CTRL(mw1_offset)); > - > bar = ntb_epf_mw_to_bar(ndev, idx); > if (bar < 0) > return bar; > > + offset = ntb_epf_mw_offset(ndev, idx); > + > if (base) > *base = pci_resource_start(ndev->ntb.pdev, bar) + offset; > > if (size) > - *size = pci_resource_len(ndev->ntb.pdev, bar) - offset; > + *size = ntb_epf_mw_size(ndev, bar) - offset; > > return 0; > } > @@ -851,6 +867,7 @@ static int ntb_epf_init_dev(struct ntb_epf_dev *ndev) > { > struct device *dev = ndev->dev; > int ret; > + int i; > > ndev->mw_count = readl(ndev->ctrl_reg + NTB_EPF_CTRL(num_mws)); > if (ndev->mw_count > NTB_EPF_MAX_MW_COUNT) { > @@ -862,6 +879,18 @@ static int ntb_epf_init_dev(struct ntb_epf_dev *ndev) > dev_err(dev, "Invalid endpoint DMA layout\n"); > return ret; > } > + if (ndev->dma.submap.size) { > + for (i = 0; i < ndev->mw_count; i++) { > + int bar = ntb_epf_mw_to_bar(ndev, i); > + > + if (bar == ndev->dma.submap.bar && > + ntb_epf_mw_size(ndev, bar) <= > + ntb_epf_mw_offset(ndev, i)) { > + dev_err(dev, "Invalid DMA/MW boundary\n"); > + return -EINVAL; > + } > + } > + } > > /* One Link interrupt and rest doorbell interrupt */ > ret = ntb_epf_init_isr(ndev, NTB_EPF_MIN_DB_COUNT + 1, > diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c > index ac83af54122f..89f828234ca7 100644 > --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c > +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c > @@ -84,12 +84,13 @@ enum epf_irq_slot { > #define MIN_DB_COUNT (EPF_IRQ_DB_START + 1) > > struct epf_ntb_dma { > + struct mutex lock; /* Serialize DMA submap and MW updates */ > struct epf_ntb_dma_ctrl ctrl; > struct dma_chan *dchan[EDMA_MAX_RD_CH]; > void *bar_scratch; > dma_addr_t bar_scratch_phys; > size_t bar_scratch_size; > - struct pci_epf_bar_submap submap[EDMA_MAX_RD_CH + 2]; > + struct pci_epf_bar_submap submap[EDMA_MAX_RD_CH + 3]; > struct pci_epf_bar_submap *reg_submap; > unsigned int num_submap; > u16 rd_ch_cnt; > @@ -229,6 +230,22 @@ static bool epf_ntb_is_bar_used(struct epf_ntb *ntb, > return false; > } > > +static u64 epf_ntb_dma_bar_offset(struct epf_ntb *ntb, enum pci_barno barno) > +{ > + unsigned int i; > + > + for (i = 0; i < ntb->num_mws; i++) > + if (ntb->epf_ntb_bar[BAR_MW1 + i] == barno) > + return ntb->mws_size[i]; > + > + return 0; > +} > + > +static bool epf_ntb_dma_shares_bar(struct epf_ntb *ntb, enum pci_barno barno) > +{ > + return ntb->dma && ntb->epf_ntb_bar[BAR_DMA] == barno; > +} > + > struct epf_ntb_dma_filter { > struct device *dev; > int chan_id; > @@ -353,6 +370,7 @@ static int epf_ntb_dw_edma_collect(struct epf_ntb *ntb, > unsigned int i; > size_t align; > u32 next = 0; > + u64 offset; > int ret; > > if (ctrl->u.dma_ctrl.reg_layout_data != EDMA_MF_EDMA_UNROLL) > @@ -371,10 +389,31 @@ static int epf_ntb_dw_edma_collect(struct epf_ntb *ntb, > if (!is_power_of_2(align)) > return -EINVAL; > > - if (epf_ntb_is_bar_used(ntb, barno) || > - pci_epc_get_next_free_bar(features, barno) != barno) > + if (barno == ntb->epf_ntb_bar[BAR_CONFIG] || > + barno == ntb->epf_ntb_bar[BAR_DB]) > return -EINVAL; > > + offset = epf_ntb_dma_bar_offset(ntb, barno); > + if (!offset && > + (epf_ntb_is_bar_used(ntb, barno) || > + pci_epc_get_next_free_bar(features, barno) != barno)) > + return -EINVAL; > + if (offset > U32_MAX) > + return -EOVERFLOW; > + if (offset && !is_power_of_2(offset)) > + return -EINVAL; > + dma->ctrl.submap.offset = offset; > + next = offset; > + if (next) { > + /* > + * submap[0] covers the MW prefix. Keep its temporary > + * target at address 0 until the MW translation is > + * installed. > + */ > + dma->submap[0].size = next; > + dma->num_submap = 1; > + } > + > dma->ctrl.magic = EPF_NTB_DMA_MAGIC; > dma->ctrl.revision = EPF_NTB_DMA_REVISION; > dma->ctrl.type = EPF_NTB_DMA_TYPE_DW_EDMA; > @@ -408,7 +447,7 @@ static int epf_ntb_dw_edma_collect(struct epf_ntb *ntb, > chan->desc_addr_lo = lower_32_bits(dma_addr); > chan->desc_addr_hi = upper_32_bits(dma_addr); > } > - dma->ctrl.submap.size = next; > + dma->ctrl.submap.size = next - dma->ctrl.submap.offset; > > dma_dev = ntb->epf->epc->dev.parent; > for (i = 0; i < dma->rd_ch_cnt; i++) { > @@ -481,6 +520,8 @@ static int epf_ntb_dma_collect(struct epf_ntb *ntb) > if (!dma) > return -ENOMEM; > > + mutex_init(&dma->lock); > + > switch (ctrl->u.dma_ctrl.reg_layout) { > case PCI_EPC_AUX_DMA_REG_LAYOUT_DW_EDMA: > ret = epf_ntb_dw_edma_collect(ntb, dma, ctrl, resources, count); > @@ -551,7 +592,7 @@ static int epf_ntb_dma_bar_init(struct epf_ntb *ntb) > return -EOPNOTSUPP; > > barno = ntb->epf_ntb_bar[BAR_DMA]; > - mapped_size = dma->ctrl.submap.size; > + mapped_size = dma->ctrl.submap.offset + dma->ctrl.submap.size; > /* > * Submaps cannot be installed until the host assigns the BAR address. > * Use address 0 for the temporary BAR Match Mode mapping, as is done > @@ -607,21 +648,25 @@ static void epf_ntb_dma_bar_clear(struct epf_ntb *ntb) > memset(bar, 0, sizeof(*bar)); > } > > -static int epf_ntb_dma_set_bar(struct epf_ntb *ntb) > +static int epf_ntb_dma_set_bar_locked(struct epf_ntb *ntb, > + const dma_addr_t *mw_addr) > { > struct pci_epf_bar_submap *old_submap; > struct epf_ntb_dma *dma = ntb->dma; > unsigned int old_num_submap; > struct pci_epf_bar *bar; > + dma_addr_t old_mw_addr; > int restore, ret; > - > - if (!dma) > - return 0; > + lockdep_assert_held(&dma->lock); > > bar = &ntb->epf->bar[ntb->epf_ntb_bar[BAR_DMA]]; > > old_submap = bar->submap; > old_num_submap = bar->num_submap; > + if (mw_addr) { > + old_mw_addr = dma->submap[0].phys_addr; > + dma->submap[0].phys_addr = *mw_addr; > + } > bar->submap = dma->submap; > bar->num_submap = dma->num_submap; > > @@ -631,6 +676,8 @@ static int epf_ntb_dma_set_bar(struct epf_ntb *ntb) > return 0; > > /* A failed dynamic update may have already removed the old mapping. */ > + if (mw_addr) > + dma->submap[0].phys_addr = old_mw_addr; > bar->submap = old_submap; > bar->num_submap = old_num_submap; > restore = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no, > @@ -642,6 +689,18 @@ static int epf_ntb_dma_set_bar(struct epf_ntb *ntb) > return ret; > } > > +static int epf_ntb_dma_set_bar(struct epf_ntb *ntb) > +{ > + struct epf_ntb_dma *dma = ntb->dma; > + > + if (!dma) > + return 0; > + > + guard(mutex)(&dma->lock); > + > + return epf_ntb_dma_set_bar_locked(ntb, NULL); > +} > + > /** > * epf_ntb_configure_mw() - Configure the Outbound Address Space for VHOST > * to access the memory window of HOST > @@ -1269,6 +1328,7 @@ static void epf_ntb_db_bar_clear(struct epf_ntb *ntb) > */ > static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) > { > + bool shared; > int ret = 0; > int i; > u64 size; > @@ -1278,22 +1338,25 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) > for (i = 0; i < ntb->num_mws; i++) { > size = ntb->mws_size[i]; > barno = ntb->epf_ntb_bar[BAR_MW1 + i]; > - > - ntb->epf->bar[barno].barno = barno; > - ntb->epf->bar[barno].size = size; > - ntb->epf->bar[barno].addr = NULL; > - ntb->epf->bar[barno].phys_addr = 0; > - ntb->epf->bar[barno].flags |= upper_32_bits(size) ? > - PCI_BASE_ADDRESS_MEM_TYPE_64 : > - PCI_BASE_ADDRESS_MEM_TYPE_32; > - > - ret = pci_epc_set_bar(ntb->epf->epc, > - ntb->epf->func_no, > - ntb->epf->vfunc_no, > - &ntb->epf->bar[barno]); > - if (ret) { > - dev_err(dev, "MW set failed\n"); > - goto err_alloc_mem; > + shared = epf_ntb_dma_shares_bar(ntb, barno); > + > + if (!shared) { > + ntb->epf->bar[barno].barno = barno; > + ntb->epf->bar[barno].size = size; > + ntb->epf->bar[barno].addr = NULL; > + ntb->epf->bar[barno].phys_addr = 0; > + ntb->epf->bar[barno].flags |= upper_32_bits(size) ? > + PCI_BASE_ADDRESS_MEM_TYPE_64 : > + PCI_BASE_ADDRESS_MEM_TYPE_32; > + > + ret = pci_epc_set_bar(ntb->epf->epc, > + ntb->epf->func_no, > + ntb->epf->vfunc_no, > + &ntb->epf->bar[barno]); > + if (ret) { > + dev_err(dev, "MW set failed\n"); > + goto err_alloc_mem; > + } > } > > /* Allocate EPC outbound memory windows to vpci vntb device */ > @@ -1310,10 +1373,11 @@ static int epf_ntb_mw_bar_init(struct epf_ntb *ntb) > return ret; > > err_set_bar: > - pci_epc_clear_bar(ntb->epf->epc, > - ntb->epf->func_no, > - ntb->epf->vfunc_no, > - &ntb->epf->bar[barno]); > + if (!shared) > + pci_epc_clear_bar(ntb->epf->epc, > + ntb->epf->func_no, > + ntb->epf->vfunc_no, > + &ntb->epf->bar[barno]); > err_alloc_mem: > epf_ntb_mw_bar_clear(ntb, i); > return ret; > @@ -1331,10 +1395,11 @@ static void epf_ntb_mw_bar_clear(struct epf_ntb *ntb, int num_mws) > > for (i = 0; i < num_mws; i++) { > barno = ntb->epf_ntb_bar[BAR_MW1 + i]; > - pci_epc_clear_bar(ntb->epf->epc, > - ntb->epf->func_no, > - ntb->epf->vfunc_no, > - &ntb->epf->bar[barno]); > + if (!epf_ntb_dma_shares_bar(ntb, barno)) > + pci_epc_clear_bar(ntb->epf->epc, > + ntb->epf->func_no, > + ntb->epf->vfunc_no, > + &ntb->epf->bar[barno]); > > pci_epc_mem_free_addr(ntb->epf->epc, > ntb->vpci_mw_phy[i], > @@ -1936,6 +2001,16 @@ static int vntb_epf_mw_set_trans(struct ntb_dev *ndev, int pidx, int idx, > dev = &ndev->dev; > barno = ntb->epf_ntb_bar[BAR_MW1 + idx]; > epf_bar = &ntb->epf->bar[barno]; > + if (epf_ntb_dma_shares_bar(ntb, barno)) { > + /* DMA submaps start after the configured MW size. */ > + if (size != ntb->mws_size[idx]) > + return -EINVAL; > + > + guard(mutex)(&ntb->dma->lock); > + > + return epf_ntb_dma_set_bar_locked(ntb, &addr); > + } > + > epf_bar->phys_addr = addr; > epf_bar->barno = barno; > epf_bar->size = size; > @@ -2134,15 +2209,17 @@ static int vntb_epf_mw_get_align(struct ntb_dev *ndev, int pidx, int idx, > resource_size_t *size_max) > { > struct epf_ntb *ntb = ntb_ndev(ndev); > + enum pci_barno barno = ntb->epf_ntb_bar[BAR_MW1 + idx]; > + u64 size = ntb->mws_size[idx]; > > if (addr_align) > *addr_align = SZ_4K; > > if (size_align) > - *size_align = 1; > + *size_align = epf_ntb_dma_shares_bar(ntb, barno) ? size : 1; > > if (size_max) > - *size_max = ntb->mws_size[idx]; > + *size_max = size; > > return 0; > } > -- > 2.54.0 >