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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1903ca044d4sm3449053c88.17.2026.10.20.22.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 22:38:23 -0700 (PDT) Date: Wed, 21 Oct 2026 11:08:16 +0530 From: Varadarajan Narayanan To: Krzysztof Kozlowski Cc: Ilia Lin , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] dt-bindings: cpufreq: qcom-nvmem: Allow generic OPP tables Message-ID: References: <20261015-opp-v1-1-f18fb6f9bae1@oss.qualcomm.com> <20261017-calm-tangerine-marmot-2e8bfc@quoll> X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="0e04jeNFWWxIqaY/" Content-Disposition: inline In-Reply-To: <20261017-calm-tangerine-marmot-2e8bfc@quoll> X-Authority-Analysis: v=2.4 cv=S/NMU4sP c=1 sm=1 tr=0 ts=6ad84fd2 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=gEfo2CItAAAA:8 a=01MFGdCsChwvBfu0fykA:9 a=CjuIK1q_8ugA:10 a=GVWKzDYot3hTMZ8E5o4A:9 a=Fk4IpSoW4aLDllm1B1p-:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAyMSBTYWx0ZWRfX3/RkJambqHCH HMMCSvvPz98d3kfYupFTdZCCcSk02IMh8Ozi0higAtCK/ki5nZf2UOT1ANXkC7OdJ7Kzr8BovZs VqKp/HRfxH/lOR5SS6D+gk9T1Nubvbet6emOJnXkxHBqFkPIFuxmBaNFGlwl6UAmkAuQHbCNtSM /uRgtBvYXhaIdR4DUB+wpybBHRnzBsv2/kEpbKyguDJLS0kOb57PXFv/m+dBcRvuWzNEr50jmHD qI3GumO1n03HDRMSUH4+Jkc/eDSMKcx+zKLdxezDWngGgLTuli0l1tBTlEkuN8wbXr0/LDX+mU0 LG/oW7L5XhbDt003kXShgH/1LE5Zx10HvPX6SdNFc4qYgAOQvAYAIxlwUgAzo+BjFHum6CGKK4L QTtolbd2d+/z7yfJmaPVNi53jFFp2Vbh6f/fW7kTAMSRIsMfRb+Yrd5fNdr9aHmpyN6dQS9g4VZ mizygmcw6zLSYqElX7w== X-Proofpoint-ORIG-GUID: greML18QjaYlXofRlUYvvMSvwkhv4SGk X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAyMSBTYWx0ZWRfX4MCKilrVwB8Y P6m/HZl1daV9T/rPP3q9vAI4Vxlhj0wjjdIwftLXhv3oxrhjtD8m/RSC1y4IzD92MbixP2TIIIk oaAe/U3tLolL0yUr2xXx1/EWYuDuqb0= X-Proofpoint-GUID: greML18QjaYlXofRlUYvvMSvwkhv4SGk X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210021 --0e04jeNFWWxIqaY/ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sat, Oct 17, 2026 at 06:45:53PM +0200, Krzysztof Kozlowski wrote: > On Thu, Oct 15, 2026 at 04:25:28PM +0530, Varadarajan Narayanan wrote: > > The OPP table node-name pattern also matches peripheral OPP tables on > > supported SoCs. However, it only handles Qualcomm CPU and level OPP > > compatibles, causing unevaluatedProperties errors for generic > > operating-points-v2 tables. > > But the select should not select them. How can I reproduce the issue? Sorry for the delay, it was a long weekend here. With the attached patch, I get the following error. $ make LLVM=-18 ARCH=arm64 CHECK_DTBS=1 qcom/ipq5210-rdp504.dtb [...] DTC [C] arch/arm64/boot/dts/qcom/ipq5210-rdp504.dtb arch/arm64/boot/dts/qcom/ipq5210-rdp504.dtb: / (qcom,ipq5210-rdp504): opp-table-qup32mhz: Unevaluated properties are not allowed ('compatible', 'opp-32000000' were unexpected) from schema $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml Thanks Varada --0e04jeNFWWxIqaY/ Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="0001-arm64-dts-qcom-ipq5210-Add-I2C-nodes.patch" >From d207f72fc23fb328aa2c3cbe1f98780667f7bf10 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Fri, 16 Oct 2026 14:24:54 +0530 Subject: [PATCH] arm64: dts: qcom: ipq5210: Add I2C nodes Add the QUPv3 I2C controller nodes for IPQ5210 and enable I2C0 with the required pin configuration on RDP504. Signed-off-by: Varadarajan Narayanan --- .../boot/dts/qcom/ipq5210-rdp504-common.dtsi | 16 +++++++ arch/arm64/boot/dts/qcom/ipq5210.dtsi | 47 +++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi index b32daa7c1559..8068dd0d2119 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504-common.dtsi @@ -59,6 +59,13 @@ vreg_misc_0p925: regulator-usb-0p925 { }; }; +&i2c0 { + pinctrl-0 = <&qup_i2c0_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + &pcie0 { pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -191,6 +198,15 @@ clock-pins { }; }; + qup_i2c0_default: qup-i2c0-default-state { + qup-i2c0-pins { + pins = "gpio20", "gpio21"; + function = "qup_se2"; + drive-strength = <6>; + bias-pull-up; + }; + }; + qup_uart1_default_state: qup-uart1-default-state { pins = "gpio38", "gpio39"; function = "qup_se1"; diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 6842ac21e05f..80050845f965 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -160,6 +160,14 @@ opp-300000000 { }; }; + i2c_opp_table_32mhz: opp-table-qup32mhz { + compatible = "operating-points-v2"; + + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -435,6 +443,45 @@ uart1: serial@1a84000 { status = "disabled"; }; + + i2c0: i2c@1a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; + + i2c1: i2c@1a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; + + i2c2: i2c@1a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; }; sdhc: mmc@7804000 { -- 2.34.1 --0e04jeNFWWxIqaY/--