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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Chao Liu From: Chao Liu via qemu development Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Oct 22, 2026 at 11:51:03PM +0800, Philippe Mathieu-Daudé wrote: > Factor riscv_excp_name() and riscv_intr_name() out of > riscv_cpu_get_trap_name(). Register riscv_excp_name() > as the CPUClass::exception_name() handler, so the common > exception logging can resolve RISCV exception codes to names. > > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Pierrick Bouvier Reviewed-by: Chao Liu Thanks, Chao > --- > target/riscv/cpu.h | 1 + > target/riscv/cpu.c | 20 ++++++++++---------- > target/riscv/tcg/op_helper.c | 2 +- > 3 files changed, 12 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b65d6319940..49a1186bdbb 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -672,6 +672,7 @@ G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, > bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > +const char *riscv_excp_name(int excp); > char *riscv_isa_string(RISCVCPU *cpu); > int riscv_cpu_max_xlen(RISCVCPUClass *mcc); > bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname); > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 08a4d14ea1f..e1652bd2a40 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -18,6 +18,7 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/cutils.h" > #include "qemu/qemu-print.h" > #include "qemu/ctype.h" > #include "qemu/log.h" > @@ -398,6 +399,11 @@ static const char * const riscv_excp_names[] = { > [RISCV_EXCP_SEMIHOST] = "semihost", > }; > > +const char *riscv_excp_name(int excp) > +{ > + return STR_ARRAY_ELEM_OR_NULL(riscv_excp_names, excp) ?: "unknown"; > +} > + > static const char * const riscv_intr_names[] = { > [IRQ_U_SOFT] = "u_software", > [IRQ_S_SOFT] = "s_software", > @@ -417,17 +423,10 @@ static const char * const riscv_intr_names[] = { > > const char *riscv_cpu_get_trap_name(uint64_t cause, bool async) > { > - if (async) { > - if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) { > - return riscv_intr_names[cause]; > - } > - } else { > - if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) { > - return riscv_excp_names[cause]; > - } > - } > + const char *name = async ? STR_ARRAY_ELEM_OR_NULL(riscv_intr_names, cause) > + : STR_ARRAY_ELEM_OR_NULL(riscv_excp_names, cause); > > - return "(unknown)"; > + return name ?: "unknown"; > } > > void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) > @@ -3128,6 +3127,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data) > &mcc->parent_phases); > > cc->class_by_name = riscv_cpu_class_by_name; > + cc->exception_name = riscv_excp_name; > cc->dump_state = riscv_cpu_dump_state; > cc->set_pc = riscv_cpu_set_pc; > cc->get_pc = riscv_cpu_get_pc; > diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c > index b8b3e43ccd5..f85f5cd83c9 100644 > --- a/target/riscv/tcg/op_helper.c > +++ b/target/riscv/tcg/op_helper.c > @@ -41,7 +41,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, > CPUState *cs = env_cpu(env); > > trace_riscv_exception(exception, > - riscv_cpu_get_trap_name(exception, false), > + riscv_excp_name(exception), > env->pc); > > cs->exception_index = exception; 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envelope-from=chao.liu@processmission.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Chao Liu From: Chao Liu via Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Oct 22, 2026 at 11:51:03PM +0800, Philippe Mathieu-Daudé wrote: > Factor riscv_excp_name() and riscv_intr_name() out of > riscv_cpu_get_trap_name(). Register riscv_excp_name() > as the CPUClass::exception_name() handler, so the common > exception logging can resolve RISCV exception codes to names. > > Signed-off-by: Philippe Mathieu-Daudé > Reviewed-by: Pierrick Bouvier Reviewed-by: Chao Liu Thanks, Chao > --- > target/riscv/cpu.h | 1 + > target/riscv/cpu.c | 20 ++++++++++---------- > target/riscv/tcg/op_helper.c | 2 +- > 3 files changed, 12 insertions(+), 11 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b65d6319940..49a1186bdbb 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -672,6 +672,7 @@ G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, > bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > +const char *riscv_excp_name(int excp); > char *riscv_isa_string(RISCVCPU *cpu); > int riscv_cpu_max_xlen(RISCVCPUClass *mcc); > bool riscv_cpu_option_set(RISCVCPU *cpu, const char *optname); > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 08a4d14ea1f..e1652bd2a40 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -18,6 +18,7 @@ > */ > > #include "qemu/osdep.h" > +#include "qemu/cutils.h" > #include "qemu/qemu-print.h" > #include "qemu/ctype.h" > #include "qemu/log.h" > @@ -398,6 +399,11 @@ static const char * const riscv_excp_names[] = { > [RISCV_EXCP_SEMIHOST] = "semihost", > }; > > +const char *riscv_excp_name(int excp) > +{ > + return STR_ARRAY_ELEM_OR_NULL(riscv_excp_names, excp) ?: "unknown"; > +} > + > static const char * const riscv_intr_names[] = { > [IRQ_U_SOFT] = "u_software", > [IRQ_S_SOFT] = "s_software", > @@ -417,17 +423,10 @@ static const char * const riscv_intr_names[] = { > > const char *riscv_cpu_get_trap_name(uint64_t cause, bool async) > { > - if (async) { > - if ((cause < ARRAY_SIZE(riscv_intr_names)) && riscv_intr_names[cause]) { > - return riscv_intr_names[cause]; > - } > - } else { > - if ((cause < ARRAY_SIZE(riscv_excp_names)) && riscv_excp_names[cause]) { > - return riscv_excp_names[cause]; > - } > - } > + const char *name = async ? STR_ARRAY_ELEM_OR_NULL(riscv_intr_names, cause) > + : STR_ARRAY_ELEM_OR_NULL(riscv_excp_names, cause); > > - return "(unknown)"; > + return name ?: "unknown"; > } > > void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext) > @@ -3128,6 +3127,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c, const void *data) > &mcc->parent_phases); > > cc->class_by_name = riscv_cpu_class_by_name; > + cc->exception_name = riscv_excp_name; > cc->dump_state = riscv_cpu_dump_state; > cc->set_pc = riscv_cpu_set_pc; > cc->get_pc = riscv_cpu_get_pc; > diff --git a/target/riscv/tcg/op_helper.c b/target/riscv/tcg/op_helper.c > index b8b3e43ccd5..f85f5cd83c9 100644 > --- a/target/riscv/tcg/op_helper.c > +++ b/target/riscv/tcg/op_helper.c > @@ -41,7 +41,7 @@ G_NORETURN void riscv_raise_exception(CPURISCVState *env, > CPUState *cs = env_cpu(env); > > trace_riscv_exception(exception, > - riscv_cpu_get_trap_name(exception, false), > + riscv_excp_name(exception), > env->pc); > > cs->exception_index = exception; > -- > 2.55.0 >