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envelope-from=chao.liu@processmission.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Oct 22, 2026 at 10:22:15PM +0800, Ralf Ramsauer wrote: > From: Ralf Ramsauer > > Whether a hart has supervisor mode is decided in two places: KVM harts > always have it, and for TCG it follows from RVS in the ISA string. > riscv_plic_hart_config_string() already spells out both cases. > > Board code needs the same answer to describe the interrupt controller, > but it should not have to reach into CPURISCVState for it. Add a helper > next to riscv_cpu_is_vendor() so the next patches can ask the CPU > instead of inspecting its internals. > > Suggested-by: Daniel Henrique Barboza > Signed-off-by: Ralf Ramsauer > Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Thanks, Chao > --- > target/riscv/cpu.c | 14 ++++++++++++++ > target/riscv/cpu.h | 1 + > 2 files changed, 15 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 08a4d14ea1..7be1c65902 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -338,6 +338,20 @@ bool riscv_cpu_is_vendor(Object *cpu_obj) > return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL; > } > > +bool riscv_cpu_has_supervisor_mode(RISCVCPU *cpu) > +{ > +#ifndef CONFIG_USER_ONLY > + /* KVM always provides supervisor mode, regardless of the ISA string */ > + if (kvm_enabled()) { > + return true; > + } > + > + return riscv_has_ext(&cpu->env, RVS); > +#else > + return false; > +#endif > +} > + > const char * const riscv_int_regnames[] = { > "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", > "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index b65d631994..a7509b0114 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -995,6 +995,7 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); > bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); > void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); > bool riscv_cpu_is_vendor(Object *cpu_obj); > +bool riscv_cpu_has_supervisor_mode(RISCVCPU *cpu); > > typedef struct isa_ext_data { > const char *name; > -- > 2.54.0 >