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Sat, 24 Oct 2026 00:16:39 -0700 (PDT) Received: from unknown748F3CBA5068 (dynamic-2a02-3100-9da9-5f01-d5f0-7ecf-afa4-4bc6.310.pool.telefonica.de. [2a02:3100:9da9:5f01:d5f0:7ecf:afa4:4bc6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ebd4d8dsm2794954f8f.36.2026.10.24.00.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 00:16:39 -0700 (PDT) Date: Sat, 24 Oct 2026 09:16:37 +0200 From: Karl Mehltretter To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Cc: Claudiu Beznea , Nicolas Ferre , Alexandre Belloni , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] pwm: atmel: Fix prescaler for periods of 2^32 clock cycles or more Message-ID: References: <20261016161221.16553-1-kmehltretter@gmail.com> X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Hi Uwe, On Thu, Oct 22, 2026 at 10:29:42AM +0100, Uwe Kleine-König wrote: > > > > if (shift > PWM_MAX_PRES) { > > dev_err(pwmchip_parent(chip), "pres exceeds the maximum value\n"); > > just above this code snippet there is: > > unsigned long long cycles = state->period; > > /* Calculate the period cycles and prescale value */ > cycles *= clkrate; > do_div(cycles, NSEC_PER_SEC); > > there is another overflow happening here if state->period * clkrate > doesn't fit into an u64. A complete fix converts that to: > > cycles = mul_u64_u64_div_u64(state->period, clkrate, NSEC_PER_SEC); > > which prevents an overflow if clkrate ≤ NSEC_PER_SEC. > The latter can be asserted by checking that at probe time after calling > clk_rate_exclusive_get(). > > The options now are I apply your patch anyhow and the above can be > addressed later, or you rework your patch to a complete fix. What is > your preference? > Good point. I took a look at this and will send an improved patch soon. Karl