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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WspYspq/lkfNwDQ0BCr6C/KXhr7yVMyBklVoUb8kMSKIWM+MM9AGJh4go+9GZD0l2tfOyHnHTE4y0rhyn+VePd16Tmme83YqJ50kDYpM0RrFzFv+JNm8gjr5Aaq8n8MzCkEklZ1bG49jH7wOsTm4Yyp3y36NyIzgjUW/kCMcsH3pw6jGiGal/FFn/+wFOQoTZ7x8UI9TfgWKheNbYZmfQCwm/FF2LrEsl+z/1LZGpCdauWCdWup+WXRf4M7XJV0ugsfP4rGz5mhjUoJ0m5ZZALnwf+l8bWyrslfIlhT3EU8h/X+c2kQ+hQX8uSTuFC8RJUcX0OZyYhokgmlrDbplHATS5m9fFod5WXfX+tEGcOKQfc8rwwIXm3AG3Z5on/kbML65Q9NI4tmTElPj+WqaQnA6rX09fwdZKBttD4GYUWEpkXV6rpwLz50Te9D0rW3I X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 19:45:46.2772 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 089db5eb-21d5-4e5c-1ec4-08df3c3e8d36 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF00022BC2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN5PR12MB9461 On Thu, Oct 15, 2026 at 08:08:48PM +0000, Mostafa Saleh wrote: > @@ -538,6 +655,7 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, > > if (is_write) { > bool last_cmdq_en = is_cmdq_enabled(smmu); > + bool last_smmu_en = is_smmu_enabled(smmu); It'd read better with smmu_was_enabled and smmu_is_enabled. > diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h > index 3903ae358555..31ab7a0335a8 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h > +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h > @@ -27,6 +27,12 @@ > * @cmdq_host: Host view of the CMDQ, only q_base, base_dma and llq used > * @cmdq_max_shift: Max shift for the CMDQ probed from HW > * @cr0: Last value of CR0 > + * @host_ste_cfg: Host stream table config > + * @host_ste_base: Host stream table base > + * @strtab_cfg: Stream table config as seen by HW > + * @strtab_dma: Physical address of the shadow stream table > + * @strtab_size: Size of the shadow stream table > + * > * @mmio_addr, @mmio_size and ARM_SMMU_FEAT_COHERENCY are filled by the host > * before de-privilege, the rest by the hypervisor driver. > */ > @@ -50,6 +56,11 @@ struct hyp_arm_smmu_v3_device { > struct arm_smmu_queue cmdq_host; > u32 cmdq_max_shift; > u32 cr0; > + dma_addr_t strtab_dma; > + size_t strtab_size; > + u64 host_ste_cfg; > + u64 host_ste_base; > + struct arm_smmu_strtab_cfg strtab_cfg; The order is different here than the kdocs. Also, it might be cleaner to group host/shadow/hw stuff separately: struct hyp_arm_smmu_v3_device { ... struct hyp_arm_smmu_v3_device_host host; struct hyp_arm_smmu_v3_device_shadow shadow; struct hyp_arm_smmu_v3_device_hw hw; // Or struct { ... } shadow; struct { ... } host; struct { ... } hw; ... }; Nicolin