Re: [PULL v2 0/9] Hppa 715 2 patches

[Helge Deller <deller@kernel.org>]

* Richard Henderson <richard.henderson@linaro.org>:
> On 10/28/26 14:06, Helge Deller wrote:
> > From: Helge Deller <deller@gmx.de>
> > 
> > The following changes since commit 73294d096cc591e122fde9e63db4739de6d84f2b:
> > 
> >    Merge tag 'qga-pull-2026-10-28' of https://github.com/kostyanf14/qemu into staging (2026-10-28 06:21:59 -0500)
> > 
> > are available in the Git repository at:
> > 
> >    https://github.com/hdeller/qemu-hppa.git tags/hppa-715-2-pull-request
> > 
> > for you to fetch changes up to 4d5bc20de77152cecb4acdf63afe0db761b2abcf:
> > 
> >    target/hppa: Update SeaBIOS-hppa to version 27 (2026-10-28 20:00:56 +0100)
> > 
> > ----------------------------------------------------------------
> > HPPA architecture patches for HP-UX 9 and 715 machine
> > 
> > A series of patches which allow to boot HP-UX 9.05 on the 715/64 machine.
> > Includes a graphics/artist fix, adjustment to 15 bits for protection IDs on
> > the 32-bit CPUs and various other parts which were missing up to now.
> > Included is also the FPU patche from Kirill A. Korinsky.
> 
> The new hppa-fpu-test fails on big-endian.

The patch below will fix the issue.
I'll include it in this patch series and resend.
Thanks!
Helge


From e0c80f0b9ca5792a91a0d14d09c3da05641d8402 Mon Sep 17 00:00:00 2001
From: Keith Monahan <keith@techtravels.org>
Date: Thu, 29 Oct 2026 17:02:33 +0100
Subject: [PATCH] target/hppa: Use 32-bit load of PSW in rsm and ssm

Since commit ebc9401a4067 ("target/hppa: Split PSW X and B into their
own field") env->psw is a uint32_t followed by psw_xb, but trans_rsm()
and trans_ssm() still read it with a 64-bit load.

On a big-endian host the low half of that load is psw_xb, so the value
passed to swap_system_mask() has none of the current system mask bits.
SSM and RSM therefore clear every PSW system mask bit except those named
in the instruction. For example, "ssm 2,r0" with PSW_Q set clears Q, and
the next interruption does not record IIR, ISR and IOR. This makes the
hppa-fpu-test dtlb-load case fail on s390x hosts.

Load only the 32-bit psw field.

Fixes: ebc9401a4067 ("target/hppa: Split PSW X and B into their own field")
Cc: qemu-stable@nongnu.org  # v9.1+
Signed-off-by: Keith Monahan <keith@techtravels.org>
Signed-off-by: Helge Deller <deller@gmx.de>

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 41300c0dd7..46c0408846 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2367,7 +2367,7 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a)
     nullify_over(ctx);
 
     tmp = tcg_temp_new_i64();
-    tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
+    tcg_gen_ld32u_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
     tcg_gen_andi_i64(tmp, tmp, ~a->i);
     gen_helper_swap_system_mask(tmp, tcg_env, tmp);
     save_gpr(ctx, a->t, tmp);
@@ -2387,7 +2387,7 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a)
     nullify_over(ctx);
 
     tmp = tcg_temp_new_i64();
-    tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
+    tcg_gen_ld32u_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw));
     tcg_gen_ori_i64(tmp, tmp, a->i);
     gen_helper_swap_system_mask(tmp, tcg_env, tmp);
     save_gpr(ctx, a->t, tmp);
> 
> 
> r~