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[95.246.144.141]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4aa80f04785sm142066715e9.4.2026.10.30.07.21.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Oct 2026 07:21:32 -0700 (PDT) Date: Fri, 30 Oct 2026 15:21:30 +0100 From: Carlo Caione To: Steffen Dirkwinkel Cc: GSS_MTK_Uboot_upstream , u-boot@lists.u-boot-project.org, Tom Rini , Ilias Apalodimas , Ryder Lee , Weijie Gao , Chunfeng Yun , Igor Belwon , David Lechner , Julien Stephan , Steffen Dirkwinkel , Chris Chen Subject: Re: [PATCH 1/2] arm: mediatek: mt8188: enable the caches in SPL Message-ID: References: <20261030-std-upstream-mt8188-spl-caches-v1-0-b45905cb19c1@beckhoff.com> <20261030-std-upstream-mt8188-spl-caches-v1-1-b45905cb19c1@beckhoff.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261030-std-upstream-mt8188-spl-caches-v1-1-b45905cb19c1@beckhoff.com> X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Fri, Oct 30, 2026 at 09:57:41 +0100, Steffen Dirkwinkel wrote: > From: Steffen Dirkwinkel > > Running through spl without the dcache is very slow, especially when > hashing or checking signatures. > > Time from the SPL banner to entering BL31 on an MT8370 module loading a > 2.7 MB FIT with SHA-256 hashes from SPI NOR, two boots each: > > FIT caches off caches on > unsigned 864.0 / 864.3 ms 95.8 / 95.8 ms > RSA-3072 signature 1903.3 / 1903.8 ms 142.0 / 142.0 ms > > Signed-off-by: Steffen Dirkwinkel > --- > arch/arm/mach-mediatek/mt8188/init.c | 14 ++++++++++++++ > arch/arm/mach-mediatek/spl.c | 7 +++++++ > 2 files changed, 21 insertions(+) > > diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c > index b2cdec8c2189..2e6aa041c38f 100644 > --- a/arch/arm/mach-mediatek/mt8188/init.c > +++ b/arch/arm/mach-mediatek/mt8188/init.c > @@ -6,6 +6,7 @@ > * Chris-QJ Chen > */ > > +#include > #include > #include > #include > @@ -47,3 +48,16 @@ int print_cpuinfo(void) > printf("CPU: MediaTek MT8188\n"); > return 0; > } > + > +#if IS_ENABLED(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) > +/* Early page tables, in DRAM unused by SPL and by U-Boot before relocation */ > +#define MT8188_EARLY_TLB_ADDR 0x4e000000 Could we use an explicitly allocated/aligned buffer for the early tables instead of 0x4e000000? That address works with the current layout, but nothing reserves it against other image loads. > + > +/* Initialize the MMU and activate the data cache in SPL */ > +void mtk_spl_enable_caches(void) > +{ > + gd->arch.tlb_addr = MT8188_EARLY_TLB_ADDR; > + gd->arch.tlb_size = PGTABLE_SIZE; > + dcache_enable(); > +} > +#endif With CONFIG_CMO_BY_VA_ONLY=y, the baseline reaches the console, but this patch stops before BL31. SPL leaves gd->ram_base/ram_size unset, so VA-based cache flushing skips RAM. Could we handle this mode, or leave early caching disabled for it? > diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c > index 125ebcd784fe..8073101e3ef6 100644 > --- a/arch/arm/mach-mediatek/spl.c > +++ b/arch/arm/mach-mediatek/spl.c > @@ -14,10 +14,17 @@ __weak int mtk_soc_early_init(void) > return 0; > } > > +__weak void mtk_spl_enable_caches(void) > +{ > +} > + > void board_init_f(ulong dummy) > { > int ret; > > + /* enable caches early */ > + mtk_spl_enable_caches(); > + The BL31 path already disables D-cache/MMU, but jump_to_image() does not, so this patch is in general fine if we are jumping to BL31 but it is not if we directly jump to BL33 for example. I tried a direct jump to a proper U-Boot from SPL and indeed both remain enabled with this patch, whereas the baseline hands over with both disabled. Could we cover the direct handoff too? > ret = spl_early_init(); > if (ret) > hang(); > > -- > 2.56.0 >