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Tue, 3 Nov 2026 05:53:54 -0800 (PST) Date: Tue, 3 Nov 2026 13:53:44 +0000 From: Yao Zi To: Hiago De Franco , u-boot@lists.u-boot-project.org, Yao Zi Cc: Tom Rini , Simon Glass , Alper Nebi Yasak , Marek Vasut , Tim Ouyang , Leo Liang , Kongyang Liu , Neha Malcom Francis , Bin Liu , Quentin Schulz , Andrei Lalaev , Zhuxu Ran , Udit Kumar Subject: Re: [PATCH 2/8] riscv: cv1800b: add SPL support Message-ID: References: <20261021-milkv-duo-spl-v1-0-ee7618860237@baylibre.com> <20261021-milkv-duo-spl-v1-2-ee7618860237@baylibre.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261021-milkv-duo-spl-v1-2-ee7618860237@baylibre.com> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/293.698.2 X-ZohoMailClient: External X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, Oct 21, 2026 at 09:54:18AM -0300, Hiago De Franco wrote: > Add SUPPORT_SPL and SPL_CPU. > > harts_early_init() enables the C906 caches and T-HEAD ISA extensions. > > Signed-off-by: Hiago De Franco > --- > arch/riscv/cpu/cv1800b/Kconfig | 2 ++ > arch/riscv/cpu/cv1800b/Makefile | 4 ++++ > arch/riscv/cpu/cv1800b/spl.c | 31 +++++++++++++++++++++++++++++++ > 3 files changed, 37 insertions(+) ... > diff --git a/arch/riscv/cpu/cv1800b/spl.c b/arch/riscv/cpu/cv1800b/spl.c > new file mode 100644 > index 00000000000..6fd62d66da7 > --- /dev/null > +++ b/arch/riscv/cpu/cv1800b/spl.c > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (c) 2026, Hiago De Franco > + * > + * CSR setup based on the Sophgo FSBL (https://github.com/sophgo/fsbl), > + * lib/cpu/riscv/bl2_entrypoint.S. > + */ > + > +#include > +#include > + > +#define CSR_MCOR 0x7c2 > +#define CSR_MCOR_CACHE_INV BIT(4) > +#define CSR_MCOR_CACHE_SEL_BOTH (BIT(1) | BIT(0)) > +#define CSR_MHCR 0x7c1 > +#define CSR_MHCR_DE BIT(1) > +#define CSR_MHCR_IE BIT(0) MHCR-related stuff looks the same on both C906 and C910 (the TH1520 platform). I did a quick check for C908[1] (used in K230) and C920[2] (used in SG2042), all of them have DE/IE in MHCR (CSR 0x7c1), so I think it makes sense to move th1520/cache.c to something like lib/thead_cache.c to re-use it for your series, reducing some code duplication. Regards, Yao Zi [1]: https://github.com/OctopusET/XuanTie-C908-docs/blob/master/XuanTie-C908-UserManual_xrvm_20240530.pdf [2]: https://www.xmosc.org.cn/UserFiles/upload/file/20251230/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C_Rev.09_20251114.pdf