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Tue, 3 Nov 2026 19:56:44 -0800 (PST) Date: Wed, 4 Nov 2026 03:56:32 +0000 From: Yao Zi To: Hiago De Franco , u-boot@lists.u-boot-project.org, Yao Zi Cc: Tom Rini , Simon Glass , Alper Nebi Yasak , Marek Vasut , Tim Ouyang , Leo Liang , Kongyang Liu , Neha Malcom Francis , Bin Liu , Quentin Schulz , Andrei Lalaev , Zhuxu Ran , Udit Kumar Subject: Re: [PATCH 4/8] board: sophgo: milkv_duo: add SPL support Message-ID: References: <20261021-milkv-duo-spl-v1-0-ee7618860237@baylibre.com> <20261021-milkv-duo-spl-v1-4-ee7618860237@baylibre.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261021-milkv-duo-spl-v1-4-ee7618860237@baylibre.com> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/293.744.82 X-ZohoMailClient: External X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, Oct 21, 2026 at 09:54:20AM -0300, Hiago De Franco wrote: > Wire up SPL for the Milk-V Duo so it no longer depends on the vendor > FSBL. > > The SPL uses the BootROM ROMAPI to load the FIT image with OpenSBI, > U-Boot and the device tree, from offset 0x40000 of fip.bin. > > The BootROM loads the SPL into the 100 KiB VC SRAM at 0x3bc00000 and > jumps past the 32-byte BL2 header, so SPL_TEXT_BASE is 0x3bc00020. > SPL_MAX_SIZE (0x13fe0) is exactly SPL_BSS_START_ADDR (0x3bc14000) minus > SPL_TEXT_BASE, so the SPL image cannot grow into its own BSS. > SPL_BSS_MAX_SIZE (0x1000) caps that 4 KiB BSS, ending at 0x3bc15000, and > SPL_STACK (0x3bc19000) is the end of the SRAM, leaving 16 KiB below it > for the stack, the pre-relocation malloc_f pool (SPL_SYS_MALLOC_F_LEN, 8 > KiB) and the global data, as the generic SPL board_init_f flow expects. Thanks for the helpful explanation, I think it would be better to add some documentation for the SoC bootflow. > In DRAM, SPL_OPENSBI_LOAD_ADDR (0x80000000) is the base of RAM: the > fixed link address OpenSBI's "generic" platform uses for fw_dynamic, and > the load address given to it in the FIT. SPL_CUSTOM_SYS_MALLOC_ADDR > (0x81000000) moves the SPL heap into DRAM once it is up, 16 MiB in, > clear of SYS_LOAD_ADDR (0x80080000), U-Boot's default load address, and > of TEXT_BASE (0x80200000). > > SPL_SMP is disabled, as only one hart is brought up, and > SPL_OPENSBI_SCRATCH_OPTIONS is cleared so that OpenSBI prints its boot > banner, which the default (SBI_SCRATCH_NO_BOOT_PRINTS) hides. Should we avoid this to keep aligned with other RISC-V boards? The banner, IMHO, is only meaningful for debugging purpose. > Signed-off-by: Hiago De Franco > --- > arch/riscv/dts/cv1800b-milkv-duo-u-boot.dtsi | 92 +++++++++++++++++++++++++++ > arch/riscv/include/asm/arch-cv1800b/rom_api.h | 36 +++++++++++ > board/sophgo/milkv_duo/Kconfig | 5 ++ > board/sophgo/milkv_duo/MAINTAINERS | 5 +- > board/sophgo/milkv_duo/Makefile | 1 + > board/sophgo/milkv_duo/spl.c | 76 ++++++++++++++++++++++ > configs/milkv_duo_defconfig | 18 ++++++ > 7 files changed, 232 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/dts/cv1800b-milkv-duo-u-boot.dtsi b/arch/riscv/dts/cv1800b-milkv-duo-u-boot.dtsi > new file mode 100644 > index 00000000000..7f9a7a03c5d > --- /dev/null > +++ b/arch/riscv/dts/cv1800b-milkv-duo-u-boot.dtsi > @@ -0,0 +1,92 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2026, Hiago De Franco > + */ ... > +&uart0 { > + bootph-pre-ram; > + clock-frequency = <25000000>; The upstream UART 8250 binding disallows clocks and clock-frequency to co-exist, and with current Linux drivers, it does cause issues, see this series[1]. If you worry about the burden of introducing clock related stuff to SPL, consider define CFG_SYS_NS16550_CLK in the board configuration header instead. ... Best regards, Yao Zi [1]: https://lore.kernel.org/all/20250623093445.62327-1-ziyao@disroot.org/