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Received: by smtp.zohomail.com with SMTPS id 1793765980477903.7168983227309; Tue, 3 Nov 2026 20:19:40 -0800 (PST) Date: Wed, 4 Nov 2026 04:19:33 +0000 From: Yao Zi To: Hiago De Franco , u-boot@lists.u-boot-project.org, Yao Zi Cc: Tom Rini , Simon Glass , Alper Nebi Yasak , Marek Vasut , Tim Ouyang , Leo Liang , Kongyang Liu , Neha Malcom Francis , Bin Liu , Quentin Schulz , Andrei Lalaev , Zhuxu Ran , Udit Kumar Subject: Re: [PATCH 5/8] board: sophgo: milkv_duo: initialize PLLs in SPL Message-ID: References: <20261021-milkv-duo-spl-v1-0-ee7618860237@baylibre.com> <20261021-milkv-duo-spl-v1-5-ee7618860237@baylibre.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261021-milkv-duo-spl-v1-5-ee7618860237@baylibre.com> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/293.744.82 X-ZohoMailClient: External X-BeenThere: u-boot@lists.u-boot-project.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: U-Boot discussion List-Archive: List-Post: List-Help: List-Subscribe: , X-Spam-Status: No, score=-18.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SPF_HELO_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed, Oct 21, 2026 at 09:54:21AM -0300, Hiago De Franco wrote: > DDR training runs from the XTAL, before the PLLs are configured, so add > PLL setup after it in board_init_f(). > > The sequence bypasses all clocks to the XTAL, reprograms the APLL, > DISPPLL, CAM0PLL, CAM1PLL, MIPIMPLL, MPLL and TPLL synthesizers and > their derived dividers, waits for lock, then switches every clock from > the XTAL bypass to its PLL source. It is ported from the Sophgo FSBL > (plat/cv180x/platform.c), https://github.com/sophgo/fsbl. I'm worried about code duplication since we already have a driver with more features under clk/sophgo. I think this setup work doesn't have to be done in the SPL stage? If so, I'll suggest delaying the work to proper U-Boot or even the kernel, with assigned-clock-rates/assigned-clock-parents for re-using existing clock driver. > Signed-off-by: Hiago De Franco > --- > board/sophgo/milkv_duo/spl.c | 123 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 123 insertions(+) > > diff --git a/board/sophgo/milkv_duo/spl.c b/board/sophgo/milkv_duo/spl.c > index 3db50df0615..8b2dc2756ae 100644 > --- a/board/sophgo/milkv_duo/spl.c > +++ b/board/sophgo/milkv_duo/spl.c ... > +static void cv18xx_pll_init(void) > +{ > + int i; > + > + /* Run everything from the XTAL while the PLLs are reprogrammed */ > + writel(0xffffffff, clkgen_reg(CLK_BYP_0)); > + writel(0x0000003f, clkgen_reg(CLK_BYP_1)); > + > + /* MIPIMPLL = 900 MHz */ > + writel(0x05488101, clkgen_reg(MIPIMPLL_CSR)); > + > + writel(0x3f, clkgen_reg(PLL_G2_SSC_SYN_CTRL)); > + for (i = 0; i < ARRAY_SIZE(cv18xx_pll_csr); i++) { > + writel(cv18xx_pll_syn_set[i], > + clkgen_reg(APLL_SSC_SYN_SET + 0x10 * i)); > + clrsetbits_le32(clkgen_reg(APLL_SSC_SYN_CTRL + 0x10 * i), > + SSC_SYN_CTRL_BYPASS, SSC_SYN_CTRL_SW_UP); > + writel(cv18xx_pll_csr[i], clkgen_reg(APLL0_CSR + 4 * i)); > + } > + > + /* Power up the PLLs */ > + clrbits_le32(clkgen_reg(PLL_G2_CTRL), PLL_G2_CTRL_PD); > + > + /* MPLL = TPLL = 850 MHz */ > + writel(0x00448101, clkgen_reg(MPLL_CSR)); > + writel(0x00448101, clkgen_reg(TPLL_CSR)); > + > + for (i = 0; i < ARRAY_SIZE(cv18xx_clk_divs); i++) > + writel(cv18xx_clk_divs[i].val, > + clkgen_reg(cv18xx_clk_divs[i].off)); > + > + clrbits_le32(clkgen_reg(MIPIMPLL_D3_PD), MIPIMPLL_D3_PD_PD); > + clrbits_le32(clkgen_reg(CAM0PLL_D2_PD), CAM0PLL_D2_PD_PD); > + > + /* Wait for the PLLs to lock */ > + udelay(200); If I read the datasheet correctly, the pll_g2_status register have bits indicating PLL's locking status. We should probably poll for these bits instead. > + /* > + * C906 clocks from the *_0 dividers, then switch every clock from the > + * XTAL to its PLL source. > + */ > + writel(CLK_SEL_0_C906_0 | CLK_SEL_0_C906_1, clkgen_reg(CLK_SEL_0)); > + writel(0, clkgen_reg(CLK_BYP_0)); > + writel(0, clkgen_reg(CLK_BYP_1)); > +} Regards, Yao Zi