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From: Catalin Marinas <catalin.marinas@arm.com>
To: michael.reeves077@gmail.com
Cc: Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
	Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Myria Sarvay <myrialsarvay@gmail.com>,
	Yureka Lilian <yureka@cyberchaos.dev>,
	Fuad Tabba <fuad.tabba@linux.dev>,
	Joey Gouly <joey.gouly@arm.com>,
	Steffen Eiden <seiden@linux.ibm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	Sven Peter <sven@kernel.org>, Janne Grunau <j@jannau.net>,
	Neal Gompa <neal@gompa.dev>,
	asahi@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] arm64: Add CPU part numbers for newer Apple Silicon CPUs
Date: Wed, 4 Nov 2026 16:29:27 +0000	[thread overview]
Message-ID: <autdZ07WVQ0MMR3A@arm.com> (raw)
In-Reply-To: <20261021-apple-m3-m4-kvm-v2-1-04905152cc2a@gmail.com>

On Wed, Oct 21, 2026 at 10:53:20AM +1100, Michael Reeves via B4 Relay wrote:
> From: Myria Sarvay <myrialsarvay@gmail.com>
> 
> Add CPU part numbers and MIDR definitions for M3, M3 Pro, M3 Max,
> base M4, A18 Pro and M5 Pro so CPU workarounds can identify these cores.
> 
> Use the SoC codenames for M4, A18 Pro and M5 Pro, with suffixes for
> their core types, as separate core codenames are not known.
> 
> Signed-off-by: Myria Sarvay <myrialsarvay@gmail.com>
> Signed-off-by: Michael Reeves <michael.reeves077@gmail.com>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

  reply	other threads:[~2026-11-04 16:29 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-20 23:53 [PATCH v2 0/2] arm64: Add KVM support for newer Apple Silicon CPUs Michael Reeves via B4 Relay
2026-10-20 23:53 ` Michael Reeves
2026-10-20 23:53 ` [PATCH v2 1/2] arm64: Add CPU part numbers " Michael Reeves via B4 Relay
2026-10-20 23:53   ` Michael Reeves
2026-11-04 16:29   ` Catalin Marinas [this message]
2026-10-20 23:53 ` [PATCH v2 2/2] arm64: Apply existing Apple Silicon CPU workarounds to newer CPUs Michael Reeves via B4 Relay
2026-10-20 23:53   ` Michael Reeves
2026-11-04 16:29   ` Catalin Marinas

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