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t=1794200240; bh=1zNWv97CstwBNheuwZjrwa0R2kSphitL/TC9zaG/Pkw=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=N95gnPXLnpzv+UXjUpQJCQWPHnwlMCE3wfy8ChEdK4EBt37m07f/VDaAK11B2doNk DpoWmXLnxhO33o2Rq+cqHz/6ZzWH2CI/Ab9KsOobE+JX3xVTT75wULQ2YLb5lYadTv +fFW0HXQF2FStsCCbpdQMoIzPuinc28mvJ1Y1CAH9pGxmXXd/uDtWLoWkaXjWZicqs mS9AeVlEqfs/uy+GFLoSw+lYuFZeng03TFRq82FCbwpVaVIMxga88hFuR1VVt/SdGJ eiHwh7d2xs2CsPWvXC0GvHjOLiQhcO88/PK///+rvCTcwyZTUyTAhdgOWPFu3GN5ch aDiNcK/jSWjDg== Date: Mon, 9 Nov 2026 12:37:00 +0800 From: Jisheng Zhang To: yunhui cui Cc: David Laight , pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dennis@kernel.org, tj@kernel.org, cl@gentwo.org, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, martin.lau@linux.dev, eddyz87@gmail.com, memxor@gmail.com, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, bjorn@kernel.org, pulehui@huawei.com, puranjay@kernel.org, thuth@redhat.com, ajones@ventanamicro.com, ben.dooks@codethink.co.uk, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, zong.li@sifive.com, conor.dooley@microchip.com, tglx@kernel.org, debug@rivosinc.com, seanwascoding@gmail.com, andybnac@gmail.com, menglong8.dong@gmail.com, cyrilbur@tenstorrent.com, wangruikang@iscas.ac.cn, atishp@rivosinc.com, apatel@ventanamicro.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, bpf@vger.kernel.org, arnd@arndb.de, nathan@kernel.org, nick.desaulniers+lkml@gmail.com, morbo@google.com, justinstitt@google.com, qingfang.deng@siflower.com.cn, linux-arch@vger.kernel.org, llvm@lists.linux.dev, dave@stgolabs.net, emil@etsalapatis.com, ihor.solodrai@linux.dev, broonie@kernel.org Subject: Re: [External] Re: [PATCH v9 1/3] riscv: implement this_cpu operations Message-ID: References: <20261108110406.97495-1-cuiyunhui@bytedance.com> <20261108110406.97495-2-cuiyunhui@bytedance.com> <20261108213254.67805ef0@pumpkin> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Stat-Signature: 8y6dgatb3epw1wqsjr63ruy69u59hzpr X-Rspam-User: X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: E3E9CA0007 X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_PASS,SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-HE-Tag: 1794200240-1852 X-HE-Meta: U2FsdGVkX1+XTJIvkq+5+e/btUph/+f4oyjIKI4VHDkCRf+1elvQkwJZ2bz0jklvTB+hv7PgiS1px+R2S0+1fMSg0vPpGe0kFaSBJsFRA5OP0uPnPvCBosZxIsbjzF9x8p4OPGqfDHN31vjdwHvvyOutwqRV9MrDA7J/DoFx5xMcXapnJXKJc87beH4MwkrFo04CI+1svGJvCcailVxj4olySbYNS+aPV8027G6VxTMRBeW0Y7AVA1q2wQy/JSpCyim7S2q522nahFWU7wK2Ap2QFDpPMH5j4s3FmkvLzh0KGCTdN1JJQj/Fwq8hI8lKzGe/1fL5kgu5TSH6bZq5LEKL3QTDP/SgQUv/I1ikMjcjFLKqoiCSAufd+0tDH6BpobgjrLLDYYSFihzY56AX71Ei1Xvk+PXgyhDRdZn+GZRpwaqb3QP5N8e9bTeSEU4w2ScNfeg53EmKK+k4pSTpKOien3HmAujj2PVTbLzvV45JqQ/X8noCJVgCIdIs4noRDMrr1+PLoHyycsQFvUA+JcVpWuMwZpdzotVNR3fIbd0Ct7X+WGfsqOLCmpgPlpwFawQreind5BLbhk/BHlFQj1+7j18l7/fOjMeZ8jAcQIbHjXqrMZfqJFmcoDC/96pysG2QMm3egrhhv3Bpl7XFgQLB5NzwLpJRHH8OtiwnRd65DE/l1A009SLbj+xsqzYEysNrWIo4H1MMbnYkhHCkSpSXsLEzwPpj5pvtIgGMjX3fGKo+B9XBErClQ+uRKpjd0LZsDrlPHX+7xiW+ltrjQ7sg+IepFKM07CsvtXQyQcRFG9BeQdHY/M+zz9LcEFqILX1Wz51CF05WZuiwH/2MIro9qyC7X9+DamrSFo5jnqjeg/RSS52ds1oXVAVZTai1G4L8qEt3Jfd4ZU8r9wqBZ0hq4nlmctzVjDh3Bd818bUhtpKjjmV6fPclmC4URxUG3pOeo1zhKEQyozSm3pN fEI24tk3 766lAdf5etE1vMPTa5AlBIW4MYhMqP9wPt3KUwXY/r6IxRXr1RvLCZAghfXVHdaV0Os2QHLU9sdKH7+U15h7/ZPwTrAMsMvGrO1Byg3re5/VL07l4sFD0o+Q1fOuhtoe1LA67AUNN2V8ImYE2Zk3OsW/xfEMMDXKnEZY0Zan4NyftaZchx7TUgYQtjNVOKW12JXduxyABuBTTRVkVKDVHxv1joukdGmqSlMMXfq14UcpUBrzQ0HWqsRz0gFEaIk3cejF0QaYFaGEFNB9Ql4SOGWrYRk3ghtMiOI42REkJNEwWswcmFNvgW03O7t68GRls4kETHSoClZBpRWj1rki6cMkMC/L+6blAxPBn5Jn14E92mg2/YnobkYuRrQr/+vQuoBZq3zxmp/OhZjurbz/9ZrWRqDwkg9RJUZvk/muySsLHs5F5+Kojc9gm5/T26bOnvA8rsJEMqrrPAHUgpcbfjwt8Xnu2QbTS/6O2HQHcg/knMqtmbQ31ixC+hTN8Zpw4JhRqekwPHjrbeemyzTPnZLpx+AK2LlOlcZv3 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Mon, Nov 09, 2026 at 11:47:43AM +0800, yunhui cui wrote: > Hi David, > > On Mon, Nov 9, 2026 at 5:33 AM David Laight > wrote: > > > > On Sun, 8 Nov 2026 19:04:04 +0800 > > Yunhui Cui wrote: > > > > > RISC-V has no asm/percpu.h, so this_cpu_*() read-modify-write > > > operations use generic implementations that disable local interrupts. > > > > > > Implement RISC-V-specific this_cpu operations with preemption disabled > > > to keep accesses on the current CPU. > > > > Have you looked at some of the schemes (I think arm64 has the latest, > > but also s390) that do most per-cpu ops without disabling preemption. > > In particular they save the pre-emption check when pre-emption > > is enabled. > > > > Basically the code tells the scheduler which register contains the > > per-cpu data so that it can be 'magically' flipped during a context > > switch. > > Many thanks for pointing this out and suggesting this optimization. This > is a very useful suggestion. In the common case no preemption or migration > occurs, so the preemption bookkeeping and reschedule check are unnecessary > overhead. > > Implementing this scheme for RISC-V will require additional changes beyond > the current series. If this series is otherwise acceptable, I would like > to land the current this_cpu_* support first and then prepare a follow-up > series using this approach. Hi Yunhui and David, During the merge window but before rc1, I implemented a riscv POC following arm64's preemptible this cpu scheme. Each operation records its per-cpu pointer, offset and address registers. Exception entry saves and clears this state, and a noinstr c helper repairs the saved offset and address registers on exception return after any migration. However, my PoC is based on current percpu offset. I planed to sent it out last Sunday, but then I found Yunhui sent his percpu series(which is up to v9, I didn't know this before) on Sat. So I hold on the sending. Now would it make sense to rebase the PoC on Yunhui's series patch2 and patch3, especially the percpu offset optimization? I can post an RFC with this rebased implementation. Thanks > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F381D606A321 for ; Mon, 9 Nov 2026 04:57:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=4C3VHKAm; dkim=fail reason="signature verification failed" (2048-bit key) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256 header.s=k20260515 header.b=N95gnPXL DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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Mon, 09 Nov 2026 04:57:22 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 609B560D23; Mon, 9 Nov 2026 04:57:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1152D1F0089F; Mon, 9 Nov 2026 04:57:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1794200240; bh=1zNWv97CstwBNheuwZjrwa0R2kSphitL/TC9zaG/Pkw=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=N95gnPXLnpzv+UXjUpQJCQWPHnwlMCE3wfy8ChEdK4EBt37m07f/VDaAK11B2doNk DpoWmXLnxhO33o2Rq+cqHz/6ZzWH2CI/Ab9KsOobE+JX3xVTT75wULQ2YLb5lYadTv +fFW0HXQF2FStsCCbpdQMoIzPuinc28mvJ1Y1CAH9pGxmXXd/uDtWLoWkaXjWZicqs mS9AeVlEqfs/uy+GFLoSw+lYuFZeng03TFRq82FCbwpVaVIMxga88hFuR1VVt/SdGJ eiHwh7d2xs2CsPWvXC0GvHjOLiQhcO88/PK///+rvCTcwyZTUyTAhdgOWPFu3GN5ch aDiNcK/jSWjDg== Date: Mon, 9 Nov 2026 12:37:00 +0800 From: Jisheng Zhang To: yunhui cui Cc: David Laight , pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dennis@kernel.org, tj@kernel.org, cl@gentwo.org, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, martin.lau@linux.dev, eddyz87@gmail.com, memxor@gmail.com, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, bjorn@kernel.org, pulehui@huawei.com, puranjay@kernel.org, thuth@redhat.com, ajones@ventanamicro.com, ben.dooks@codethink.co.uk, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, zong.li@sifive.com, conor.dooley@microchip.com, tglx@kernel.org, debug@rivosinc.com, seanwascoding@gmail.com, andybnac@gmail.com, menglong8.dong@gmail.com, cyrilbur@tenstorrent.com, wangruikang@iscas.ac.cn, atishp@rivosinc.com, apatel@ventanamicro.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, bpf@vger.kernel.org, arnd@arndb.de, nathan@kernel.org, nick.desaulniers+lkml@gmail.com, morbo@google.com, justinstitt@google.com, qingfang.deng@siflower.com.cn, linux-arch@vger.kernel.org, llvm@lists.linux.dev, dave@stgolabs.net, emil@etsalapatis.com, ihor.solodrai@linux.dev, broonie@kernel.org Subject: Re: [External] Re: [PATCH v9 1/3] riscv: implement this_cpu operations Message-ID: References: <20261108110406.97495-1-cuiyunhui@bytedance.com> <20261108110406.97495-2-cuiyunhui@bytedance.com> <20261108213254.67805ef0@pumpkin> X-Archived-By: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" X-Spam-Status: No, score=-3.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 T24gTW9uLCBOb3YgMDksIDIwMjYgYXQgMTE6NDc6NDNBTSArMDgwMCwgeXVuaHVpIGN1aSB3cm90 ZToKPiBIaSBEYXZpZCwKPiAKPiBPbiBNb24sIE5vdiA5LCAyMDI2IGF0IDU6MzPigK9BTSBEYXZp ZCBMYWlnaHQKPiA8ZGF2aWQubGFpZ2h0LmxpbnV4QGdtYWlsLmNvbT4gd3JvdGU6Cj4gPgo+ID4g T24gU3VuLCAgOCBOb3YgMjAyNiAxOTowNDowNCArMDgwMAo+ID4gWXVuaHVpIEN1aSA8Y3VpeXVu aHVpQGJ5dGVkYW5jZS5jb20+IHdyb3RlOgo+ID4KPiA+ID4gUklTQy1WIGhhcyBubyBhc20vcGVy Y3B1LmgsIHNvIHRoaXNfY3B1XyooKSByZWFkLW1vZGlmeS13cml0ZQo+ID4gPiBvcGVyYXRpb25z IHVzZSBnZW5lcmljIGltcGxlbWVudGF0aW9ucyB0aGF0IGRpc2FibGUgbG9jYWwgaW50ZXJydXB0 cy4KPiA+ID4KPiA+ID4gSW1wbGVtZW50IFJJU0MtVi1zcGVjaWZpYyB0aGlzX2NwdSBvcGVyYXRp b25zIHdpdGggcHJlZW1wdGlvbiBkaXNhYmxlZAo+ID4gPiB0byBrZWVwIGFjY2Vzc2VzIG9uIHRo ZSBjdXJyZW50IENQVS4KPiA+Cj4gPiBIYXZlIHlvdSBsb29rZWQgYXQgc29tZSBvZiB0aGUgc2No ZW1lcyAoSSB0aGluayBhcm02NCBoYXMgdGhlIGxhdGVzdCwKPiA+IGJ1dCBhbHNvIHMzOTApIHRo YXQgZG8gbW9zdCBwZXItY3B1IG9wcyB3aXRob3V0IGRpc2FibGluZyBwcmVlbXB0aW9uLgo+ID4g SW4gcGFydGljdWxhciB0aGV5IHNhdmUgdGhlIHByZS1lbXB0aW9uIGNoZWNrIHdoZW4gcHJlLWVt cHRpb24KPiA+IGlzIGVuYWJsZWQuCj4gPgo+ID4gQmFzaWNhbGx5IHRoZSBjb2RlIHRlbGxzIHRo ZSBzY2hlZHVsZXIgd2hpY2ggcmVnaXN0ZXIgY29udGFpbnMgdGhlCj4gPiBwZXItY3B1IGRhdGEg c28gdGhhdCBpdCBjYW4gYmUgJ21hZ2ljYWxseScgZmxpcHBlZCBkdXJpbmcgYSBjb250ZXh0Cj4g PiBzd2l0Y2guCj4gCj4gTWFueSB0aGFua3MgZm9yIHBvaW50aW5nIHRoaXMgb3V0IGFuZCBzdWdn ZXN0aW5nIHRoaXMgb3B0aW1pemF0aW9uLiBUaGlzCj4gaXMgYSB2ZXJ5IHVzZWZ1bCBzdWdnZXN0 aW9uLiBJbiB0aGUgY29tbW9uIGNhc2Ugbm8gcHJlZW1wdGlvbiBvciBtaWdyYXRpb24KPiBvY2N1 cnMsIHNvIHRoZSBwcmVlbXB0aW9uIGJvb2trZWVwaW5nIGFuZCByZXNjaGVkdWxlIGNoZWNrIGFy ZSB1bm5lY2Vzc2FyeQo+IG92ZXJoZWFkLgo+IAo+IEltcGxlbWVudGluZyB0aGlzIHNjaGVtZSBm b3IgUklTQy1WIHdpbGwgcmVxdWlyZSBhZGRpdGlvbmFsIGNoYW5nZXMgYmV5b25kCj4gdGhlIGN1 cnJlbnQgc2VyaWVzLiBJZiB0aGlzIHNlcmllcyBpcyBvdGhlcndpc2UgYWNjZXB0YWJsZSwgSSB3 b3VsZCBsaWtlCj4gdG8gbGFuZCB0aGUgY3VycmVudCB0aGlzX2NwdV8qIHN1cHBvcnQgZmlyc3Qg YW5kIHRoZW4gcHJlcGFyZSBhIGZvbGxvdy11cAo+IHNlcmllcyB1c2luZyB0aGlzIGFwcHJvYWNo LgoKSGkgWXVuaHVpIGFuZCBEYXZpZCwKCkR1cmluZyB0aGUgbWVyZ2Ugd2luZG93IGJ1dCBiZWZv cmUgcmMxLCBJIGltcGxlbWVudGVkIGEgcmlzY3YgUE9DCmZvbGxvd2luZyBhcm02NCdzIHByZWVt cHRpYmxlIHRoaXMgY3B1IHNjaGVtZS4gRWFjaCBvcGVyYXRpb24gcmVjb3JkcwppdHMgcGVyLWNw dSBwb2ludGVyLCBvZmZzZXQgYW5kIGFkZHJlc3MgcmVnaXN0ZXJzLiBFeGNlcHRpb24gZW50cnkg c2F2ZXMKYW5kIGNsZWFycyB0aGlzIHN0YXRlLCBhbmQgYSBub2luc3RyIGMgaGVscGVyIHJlcGFp cnMgdGhlIHNhdmVkIG9mZnNldAphbmQgYWRkcmVzcyByZWdpc3RlcnMgb24gZXhjZXB0aW9uIHJl dHVybiBhZnRlciBhbnkgbWlncmF0aW9uLgoKSG93ZXZlciwgbXkgUG9DIGlzIGJhc2VkIG9uIGN1 cnJlbnQgcGVyY3B1IG9mZnNldC4KCkkgcGxhbmVkIHRvIHNlbnQgaXQgb3V0IGxhc3QgU3VuZGF5 LCBidXQgdGhlbiBJIGZvdW5kIFl1bmh1aSBzZW50CmhpcyBwZXJjcHUgc2VyaWVzKHdoaWNoIGlz IHVwIHRvIHY5LCBJIGRpZG4ndCBrbm93IHRoaXMgYmVmb3JlKSBvbiBTYXQuClNvIEkgaG9sZCBv biB0aGUgc2VuZGluZy4KCk5vdyB3b3VsZCBpdCBtYWtlIHNlbnNlIHRvIHJlYmFzZSB0aGUgUG9D IG9uIFl1bmh1aSdzIHNlcmllcyBwYXRjaDIgYW5kCnBhdGNoMywgZXNwZWNpYWxseSB0aGUgcGVy Y3B1IG9mZnNldCBvcHRpbWl6YXRpb24/IEkgY2FuIHBvc3QgYW4gUkZDCndpdGggdGhpcyByZWJh c2VkIGltcGxlbWVudGF0aW9uLgoKVGhhbmtzCj4gCj4gCj4gX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX18KPiBsaW51eC1yaXNjdiBtYWlsaW5nIGxpc3QKPiBs aW51eC1yaXNjdkBsaXN0cy5pbmZyYWRlYWQub3JnCj4gaHR0cDovL2xpc3RzLmluZnJhZGVhZC5v cmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1yaXNjdgoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KbGludXgtcmlzY3YgbWFpbGluZyBsaXN0CmxpbnV4LXJp c2N2QGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1h bi9saXN0aW5mby9saW51eC1yaXNjdgo=