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[35.189.192.250]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-495974660bdsm8966088f8f.37.2026.11.09.03.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 03:30:10 -0800 (PST) Date: Mon, 9 Nov 2026 11:30:05 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com Subject: Re: [PATCH v9 14/25] iommu/arm-smmu-v3-kvm: Shadow the command queue Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-15-smostafa@google.com> X-Mailing-List: iommu@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Thu, Nov 05, 2026 at 03:54:12PM -0800, Nicolin Chen wrote: > On Thu, Oct 15, 2026 at 08:08:45PM +0000, Mostafa Saleh wrote: > > At boot, allocate a command queue per SMMU which is used as a shadow > > by the hypervisor. > > > > The command queue size is 64K which is more than enough, as the > > hypervisor would consume all the entries per a command queue prod > > write, which means it can handle up to 4096 at a time. > > > > Then, the host command queue needs to be pinned in a shared state, so > > it can't be donated to VMs, and avoid tricking the hypervisor into > > accessing them. This is done each time the command queue is enabled, > > and undone each time the command queue is disabled. > > The hypervisor won't access the host command queue when it is disabled > > from the host. > > > > Signed-off-by: Mostafa Saleh > > Reviewed-by: Nicolin Chen > > With some nits: > > > @@ -23,6 +25,15 @@ static size_t kvm_arm_smmu_cur; > > static void __init kvm_arm_smmu_array_free(void) > > { > > int order; > > + int i; > > + > > + for (i = 0 ; i < kvm_arm_smmu_cur ; ++i) { > > s/ ;/;/g Will do. > > > @@ -158,6 +268,14 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, > > break; > > /* Passthrough the register access for bisectability, handled later */ > > case ARM_SMMU_CMDQ_BASE: > > + if (is_write) { > > + /* Not allowed by the architecture */ > > + if (is_cmdq_enabled(smmu)) > > + break; > > Sashiko reported the same WARN_ON issue. You might want to confirm. > I replied to sashiko about that, this is by design as I also mentioned in patch #13. > > @@ -170,9 +288,16 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, > > break; > > > > if (is_write) { > > + bool last_cmdq_en = is_cmdq_enabled(smmu); > > Maybe cmdq_was_enabled (local) and cmdq_is_enabled (helper) Sure. Thanks, Mostafa > > > Nicolin