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Tue, 10 Nov 2026 08:23:28 -0800 (PST) Received: from linaro.org ([2a10:d582:31e:0:aa96:7f3b:af27:16e8]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c504a57085fsm131968566b.22.2026.11.10.08.23.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Nov 2026 08:23:27 -0800 (PST) Date: Tue, 10 Nov 2026 16:23:25 +0000 From: Jim MacArthur To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Subject: Re: [PATCH for-11.2 1/4] hw/intc/arm_gicv5: Use cached IRS_IST_BASER.VALID state Message-ID: References: <20261103172616.2400758-1-peter.maydell@linaro.org> <20261103172616.2400758-2-peter.maydell@linaro.org> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261103172616.2400758-2-peter.maydell@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=jim.macarthur@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Tue, Nov 03, 2026 at 05:26:13PM +0000, Peter Maydell wrote: > When the guest writes to IRS_IST_BASER we effectively cache the value > of the VALID bit in the GICv5ISTConfig valid field entry. In a few > places we check whether the IST is valid by doing a bit extract on > the register value; switch those to look at cfg->structure instead. > > Signed-off-by: Peter Maydell > --- > hw/intc/arm_gicv5.c | 7 +++---- > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c > index 5d0a50ab6aa..d0a8574916b 100644 > --- a/hw/intc/arm_gicv5.c > +++ b/hw/intc/arm_gicv5.c > @@ -1222,8 +1222,7 @@ static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value) > uint64_t l1_iste; > MemTxResult res; > > - if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) || > - !cfg->structure) { > + if (!cfg->valid || !cfg->structure) { > /* WI if no IST set up or it is not 2-level */ > return; > } > @@ -1293,7 +1292,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value) > { > GICv5Common *cs = ARM_GICV5_COMMON(s); > > - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { > + if (s->phys_lpi_config[domain].valid) { > /* If VALID is set, ADDR is RO and we can only update VALID */ > bool valid = FIELD_EX64(value, IRS_IST_BASER, VALID); > if (valid) { > @@ -1604,7 +1603,7 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset, > deposit64(cs->irs_ist_baser[domain], 32, 32, data)); > return true; > case A_IRS_IST_CFGR: > - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { > + if (s->phys_lpi_config[domain].valid) { > qemu_log_mask(LOG_GUEST_ERROR, > "guest tried to write IRS_IST_CFGR for %s config frame " > "while IST_BASER.VALID set\n", domain_name[domain]); That makes sense. Reviewed-by: Jim MacArthur