From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Biju Das <biju.das.au@gmail.com>
Cc: Ulf Hansson <ulfh@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v25 11/11] mmc: renesas_sdhi: Add RZ/G3L SDHI support
Date: Wed, 11 Nov 2026 12:24:14 +0100 [thread overview]
Message-ID: <avRQWlS4DsBDU5c5@shikoro> (raw)
In-Reply-To: <20261028-rzg3l_sdhi-v25-11-57f16691c2ed@bp.renesas.com>
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On Wed, Oct 28, 2026 at 12:51:28PM +0000, Biju Das wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The RZ/G3L SDHI is close to existing variants but differs in three
> ways the driver can't handle today:
>
> - It has an 11-bit clock divider. The upper bits live in CLK_CTL
> bits [17:16], so the register must be written with a 32-bit access
> on this SoC.
> - Tuning needs a second HW adjustment register (HWADJ2), programmed
> together with TMPPORT2.
> - HWADJ4 must be cleared when tuning starts.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
I like the renesas_sdhi_sclken() helper.
All review done, congrats! I will run some tests on R-Car hardware in
a few minutes.
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next prev parent reply other threads:[~2026-11-11 11:24 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-28 12:51 [PATCH v25 00/11] Add Renesas RZ/G3L SD/eMMC support Biju Das
2026-10-28 12:51 ` [PATCH v25 01/11] dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC Biju Das
2026-10-28 12:51 ` [PATCH v25 02/11] mmc: renesas_sdhi: Clean up whitespace and add OF table sentinels Biju Das
2026-10-28 12:51 ` [PATCH v25 03/11] mmc: renesas_sdhi: Add clk_mask to support wider clock dividers Biju Das
2026-11-11 10:07 ` Wolfram Sang
2026-10-28 12:51 ` [PATCH v25 04/11] mmc: renesas_sdhi: Add max_divider field to support SoC-specific clock ranges Biju Das
2026-11-11 10:13 ` Wolfram Sang
2026-10-28 12:51 ` [PATCH v25 05/11] mmc: renesas_sdhi: Add SDHI_SD_CLK_CTL_DIV1 macro for 1/1 option Biju Das
2026-10-28 12:51 ` [PATCH v25 06/11] mmc: renesas_sdhi: Make clock divider mask configurable Biju Das
2026-11-11 10:14 ` Wolfram Sang
2026-10-28 12:51 ` [PATCH v25 07/11] mmc: renesas_sdhi: Add tuning delay support for RZ/G2L Biju Das
2026-11-11 10:28 ` Wolfram Sang
2026-10-28 12:51 ` [PATCH v25 08/11] mmc: renesas_sdhi: Add TMIO_MMC_INTERNAL_DIVIDER flag Biju Das
2026-11-11 10:32 ` Wolfram Sang
2026-10-28 12:51 ` [PATCH v25 09/11] mmc: renesas_sdhi: Add optional axis/axim reset controls Biju Das
2026-10-28 12:51 ` [PATCH v25 10/11] mmc: renesas_sdhi: Add write32_hook for CTL_SD_CARD_CLK_CTL register writes Biju Das
2026-11-11 10:36 ` Wolfram Sang
2026-10-28 12:51 ` [PATCH v25 11/11] mmc: renesas_sdhi: Add RZ/G3L SDHI support Biju Das
2026-11-11 11:24 ` Wolfram Sang [this message]
2026-11-11 11:48 ` [PATCH v25 00/11] Add Renesas RZ/G3L SD/eMMC support Wolfram Sang
2026-11-11 14:42 ` Biju Das
2026-11-11 12:37 ` Ulf Hansson
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