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Thu, 12 Nov 2026 17:14:42 -0800 (PST) Received: from localhost ([2a00:79e0:2e7c:8:616b:3e06:cec4:c2f9]) by smtp.gmail.com with UTF8SMTPSA id a92af1059eb24-1b50309b2b5sm2265698c88.1.2026.11.12.17.14.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Nov 2026 17:14:41 -0800 (PST) Date: Thu, 12 Nov 2026 17:14:38 -0800 From: Brian Norris To: Krzysztof Kozlowski Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stephen Boyd , Brian Masney , Jerome Brunet , Thomas Gleixner , Ulf Hansson , Philipp Zabel , Peter Griffin , devicetree@vger.kernel.org, Tudor Ambarus , =?iso-8859-1?Q?Andr=E9?= Draszik , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Radu Rendec , linux-arm-kernel@lists.infradead.org, Mariano Marciello , Douglas Anderson , linux-clk@vger.kernel.org, Jakub =?utf-8?B?R8WCb3dhY2tp?= Subject: Re: [PATCH 2/9] dt-bindings: soc: google: Add Google Tensor CPM binding Message-ID: References: <20261026214359.3122870-1-briannorris@chromium.org> <20261026144346.2.Ib692ddd35c1dbea1757d9b1db6c1c7e938fc4ea6@changeid> <20261028-rapid-daffodil-rat-0adc6a@quoll> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261112_171444_030458_A14196F8 X-CRM114-Status: GOOD ( 46.77 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Hi Krzysztof, On Thu, Nov 05, 2026 at 07:54:22PM +0100, Krzysztof Kozlowski wrote: > On 03/11/2026 03:36, Brian Norris wrote: > > On Wed, Oct 28, 2026 at 02:19:23PM +0100, Krzysztof Kozlowski wrote: > >> On Mon, Oct 26, 2026 at 02:43:40PM -0700, Brian Norris wrote: > > > >>> --- /dev/null > >>> +++ b/include/dt-bindings/interrupt-controller/irq-cpm-google.h > >>> @@ -0,0 +1,16 @@ > >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > >>> +/* > >>> + * This header provides constants for CPM IRQ. > >>> + * > >>> + * Copyright 2025-2026 Google LLC > >>> + * > >>> + */ > >>> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_CPM_H > >>> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_CPM_H > >>> + > >>> +#define CPM_IRQ_RTC_ALARM_NO 0 > >> > >> Keep naming consistent. Clocks has _CLK suffix, so this should not use > >> prefix. > >> > >> > >>> +#define CPM_IRQ_AOC_MIN 7 > >> > >> Anyway, ABI constants should be indexed from 0 and incremented by 1. > > > > What do you mean by this? Do I need to make up names for the > > unused IDs between 0 and 7? On an initial search, I don't believe they > > have any meaning at all. Does that mean I should make up some kind of > > "RESERVED_" naming here? > > No, I meant CPM_IRQ_AOC_MIN is 1. > > > > > Between 7 and 156, these are just ... 150 different "service numbers" > > within the AOC (Always On Connectivity) subsystem. I can name them > > AOC_0, AOC_1, ... AOC_149 if that helps. > > > > Or are you suggesting that I pack the actual use cases (so, 0 and 7-157) > > into 0-151? I thought it was valuable to directly use the firmware > > indexing where possible; if I change those, then the indexing loses its > > inherent meaning, and we also have to add another layer of translation. > > We do not use hardware numbers as bindings and ABI, because that's > pointless - no benefits, only risks. Similarly you do not define GIC > interrupt numbers, pinctrl pin numbers, MMIO addresses as bindings. None > of these bind anything between DTS and software, so not a binding. OK, I see your point about the distinction between hardware numbers and bindings. So are firmware-protocol-defined numbers more like hardware numbers or bindings? > There are some exceptions like SCMI firmware, but that's not the case here. It's funny you mention that, because that's exactly what Jerome compared this to in the clk, reset, and pmdomain portions. These values are used literally in the firmware interface, so I'd consider them very similar to SCMI firmware protocol IDs (and, not that different to hardware IDs, if you consider the "firmware" as essentially unchangeable). And if I change this to *not* be literal firmware IDs, then Jerome's suggestions on patch 5 (to imitate SCMI, and to defer more control to the firmware) become more difficult. If I do keep these as literal firmware IDs: does that mean you'd prefer these not be in dt-bindings/? Many of them (especially the IRQ IDs you're pointing at) are not needed at all in the kernel side; they serve more as naming documentation than anything else. I can just inline them into the DTS. But I'd prefer having macro names for LPCM IDs and similar, as it vastly helps DTS readability. > > > >>> +#define CPM_IRQ_AOC_MAX 156 > >>> +#define CPM_IRQ_AP_GDMC_WAKE 157 > >>> + > >>> +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_CPM_H */ > > > > > >>> --- /dev/null > >>> +++ b/include/dt-bindings/soc/google,lga-lpcm.h > >>> @@ -0,0 +1,54 @@ > >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > >>> + > >>> +#ifndef __DT_BINDINGS_SOC_GOOGLE_LGA_LPCM_H > >>> +#define __DT_BINDINGS_SOC_GOOGLE_LGA_LPCM_H > >>> + > >>> +/* > >>> + * LPCM IDs of each SSWRP. > >>> + */ > >>> +#define LGA_LPCM_CPM 0 > >> > >> What are all these? > > > > The binding doc says: > > > > Each reset is specified by an LPCM ID (cell 1) and a reset ID (cell 2). > > See for LPCM IDs and > > for reset IDs. > > > > and > > > > Each clock is specified by an LPCM ID (cell 1) and a clock ID (cell > > 2). See for LPCM IDs and > > for clock IDs. > > > > These are the IDs used in the firmware interface to talk about these > > things, as many of the SoC resources involved (clocks, resets, power > > domains) are grouped in this way (by subsystem (SSWRP / LPCM), and then > > with indexing within each subsystem). > > > > In reading again, I see that the definitions and explanation of these > > terms and the SoC organization are split a bit between the pmdomain > > commit message and the binding doc. Where would you prefer I elaborate > > more? In the binding doc, the comments here, or both? > > I just try to understand their placement. Bindings should not be in the > soc directory, except a few things without clear subsystem owner. If > this applies for both clocks and resets, maybe this could be firmware, Maybe firmware, maybe power? LPCM is "Local Power and Clock Manager", and I believe there's essentially 1 LPCM (microcontroller) within each top-level power domain. Brian > but another point is that you should not need these in DTS. Somehow you > split one clock/reset ID into two - LPCM ID and clock/reset ID. Just > don't, unless you want to say that for example LSION_CLI16_UART_CLK is > in multiple LPCM places?