Re: [PATCH 3/4] clk: qcom: Add an option to poll for GDSCR GDSC_POWER_ON bit

[Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>]

Hi Reza,

On 9/10/2026 3:11 PM, Reza Kurniawan wrote:
> Some SoCs such as MSM8917 poll its GDSC power domains by reading GDSCR
> directly, as opposed to GDSCR + CFG_GDSCR_OFFSET.
> Add a poll_gdscr flag to struct qcom_power_map to facilitate those SoCs.
>
> Signed-off-by: Reza Kurniawan <imkyufie@gmail.com>
Reviewed-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>
>   drivers/clk/qcom/clock-qcom.c | 24 +++++++++++++-----------
>   drivers/clk/qcom/clock-qcom.h |  1 +
>   2 files changed, 14 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 6b46d9db7..754ff4ff4 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -505,9 +505,9 @@ U_BOOT_DRIVER(qcom_reset) = {
>   static int qcom_power_set(struct power_domain *pwr, bool on)
>   {
>   	struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(pwr->dev);
> -	void __iomem *base = dev_get_priv(pwr->dev);
> +	void __iomem *base = dev_get_priv(pwr->dev), *poll_addr;
>   	const struct qcom_power_map *map;
> -	u32 value;
> +	u32 value, mask;
>   	int ret;
>   
>   	if (pwr->id >= data->num_power_domains)
> @@ -527,19 +527,21 @@ static int qcom_power_set(struct power_domain *pwr, bool on)
>   
>   	writel(value, base + map->reg);
>   
> -	if (on)
> -		ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
> +	poll_addr = base + map->reg;
> +	if (map->poll_gdscr) {
> +		/* Some SOCs such as MSM8917 poll at GDSCR */
> +		ret = readl_poll_timeout(poll_addr,
>   					 value,
> -					 (value & GDSC_POWER_UP_COMPLETE) ||
> -					 (value & GDSC_PWR_ON_MASK),
> +					 (!!(value & GDSC_PWR_ON_MASK) == on),
>   					 GDSC_STATUS_POLL_TIMEOUT_US);
> -
> -	else
> -		ret = readl_poll_timeout(base + map->reg + CFG_GDSCR_OFFSET,
> +	} else {
> +		mask = on ? GDSC_POWER_UP_COMPLETE : GDSC_POWER_DOWN_COMPLETE;
> +		ret = readl_poll_timeout(poll_addr + CFG_GDSCR_OFFSET,
>   					 value,
> -					 (value & GDSC_POWER_DOWN_COMPLETE) ||
> -					 !(value & GDSC_PWR_ON_MASK),
> +					 (value & mask) ||
> +					 !!(value & GDSC_PWR_ON_MASK) == on,
>   					 GDSC_STATUS_POLL_TIMEOUT_US);
> +	}
>   
>   	if (ret == -ETIMEDOUT)
>   		printf("WARNING: GDSC %lu is stuck during power on/off\n",
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 3a4550d85..0b514cc1f 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -76,6 +76,7 @@ struct qcom_reset_map {
>   
>   struct qcom_power_map {
>   	unsigned int reg;
> +	bool poll_gdscr;
>   };
>   
>   struct clk;