From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCDC2C433FE for ; Mon, 7 Nov 2022 10:45:01 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.439277.693308 (Exim 4.92) (envelope-from ) id 1orzcV-0001P3-4P; Mon, 07 Nov 2022 10:44:47 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 439277.693308; Mon, 07 Nov 2022 10:44:47 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1orzcV-0001Ow-1X; Mon, 07 Nov 2022 10:44:47 +0000 Received: by outflank-mailman (input) for mailman id 439277; Mon, 07 Nov 2022 10:44:45 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1orzcT-0001Oq-6C for xen-devel@lists.xenproject.org; Mon, 07 Nov 2022 10:44:45 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1orzcS-0003ag-No; Mon, 07 Nov 2022 10:44:44 +0000 Received: from 54-240-197-238.amazon.com ([54.240.197.238] helo=[192.168.25.99]) by xenbits.xenproject.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1orzcS-0005UY-GN; Mon, 07 Nov 2022 10:44:44 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:From: References:Cc:To:Subject:MIME-Version:Date:Message-ID; bh=DSlAdsbIIpXcQ4Va4b6w1JeG0tSAfdhpG/PrKwQnXWY=; b=rDYMqqYUP6w5XNMdqapst3CbYT AHlF7mC9z9iyBZAHmE/zBWqcYCk6rAe1VLyA16UufZqeRgQaNpJTdZXIyVqLPGehPodIBd7oox2ZM 0mA7iVUae7y3lrXfZq2v3SJksS5qDhy68xOZs0S7Ojhtg8dehvDm/V7dZvVCFskvYIVw=; Message-ID: Date: Mon, 7 Nov 2022 10:44:42 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [XEN v2] xen/Arm: Enforce alignment check for atomic read/write Content-Language: en-US To: Ayan Kumar Halder , Ayan Kumar Halder , xen-devel@lists.xenproject.org Cc: sstabellini@kernel.org, stefanos@xilinx.com, Volodymyr_Babchuk@epam.com, bertrand.marquis@arm.com, michal.orzel@amd.com References: <20221104162355.23369-1-ayan.kumar.halder@amd.com> <062c9507-7744-0742-effb-76d2f1222a27@xen.org> <33a2d125-b7f2-3637-9dab-6b7d616fd4ff@amd.com> From: Julien Grall In-Reply-To: <33a2d125-b7f2-3637-9dab-6b7d616fd4ff@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Ayan, On 07/11/2022 10:36, Ayan Kumar Halder wrote: > > On 06/11/2022 17:54, Julien Grall wrote: >> Hi Ayan, > > Hi Julien, > > I need some clarification. > >> >> To me the title and the explaination below suggests... >> >> On 04/11/2022 16:23, Ayan Kumar Halder wrote: >>> From: Ayan Kumar Halder >>> >>> Refer ARM DDI 0487I.a ID081822, B2.2.1 >>> "Requirements for single-copy atomicity >>> >>> - A read that is generated by a load instruction that loads a single >>> general-purpose register and is aligned to the size of the read in the >>> instruction is single-copy atomic. >>> >>> -A write that is generated by a store instruction that stores a single >>> general-purpose register and is aligned to the size of the write in the >>> instruction is single-copy atomic" >>> >>> On AArch32, the alignment check is enabled at boot time by setting >>> HSCTLR.A bit. >>> ("HSCTLR, Hyp System Control Register"). >>> However in AArch64, alignment check is not enabled at boot time. >> >> ... you want to enable the alignment check on AArch64 always. > > I want to enable alignment check *only* for atomic access. > > May be I should remove this line --> "However in AArch64, alignment > check is not enabled at boot time.". > >> However, this is not possible to do because memcpy() is using >> unaligned access. > This is a non atomic access. So the commit does not apply here. Right, but your commit message refers to the alignment check on arm32. You wrote too much for someone to wonder but not enough to explain why we can't enable the alignment check on arm64. >> >> I think the commit message/title should clarify that the check is >> *only* done during debug build. IOW, there are no enforcement in >> producation build. > > AFAICS read_atomic()/write_atomic() is enabled during non debug builds > (ie CONFIG_DEBUG=n) as well. My point was that ASSERT() is a NOP in production build. So you effectively the enforcement happens only in debug build. IOW, unless you test exhaustively with a debug build, you may never notice that the access was not atomic. Cheers, -- Julien Grall