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Tue, 11 Aug 2026 00:54:09 -0700 (PDT) Message-ID: Subject: Re: [PATCH bpf-next v11 03/10] bpf: Introduce global percpu data From: Eduard Zingerman To: Leon Hwang , bpf@vger.kernel.org Cc: Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Kumar Kartikeya Dwivedi , Song Liu , Yonghong Song , Jiri Olsa , John Fastabend , Quentin Monnet , Shuah Khan , linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kernel-patches-bot@fb.com Date: Tue, 11 Aug 2026 00:54:05 -0700 In-Reply-To: <5e8cc9c2-ae36-493b-922f-0d86f253265c@linux.dev> References: <20260806163125.11172-1-leon.hwang@linux.dev> <20260806163125.11172-4-leon.hwang@linux.dev> <8ea2c2ef5a50333c84865d09c860a9617edbda9b.camel@gmail.com> <5e8cc9c2-ae36-493b-922f-0d86f253265c@linux.dev> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-10 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2026-08-11 at 12:16 +0800, Leon Hwang wrote: > On 11/8/26 07:22, Eduard Zingerman wrote: > > On Fri, 2026-08-07 at 00:31 +0800, Leon Hwang wrote: > >=20 > > ... > >=20 > > > diff --git a/kernel/bpf/fixups.c b/kernel/bpf/fixups.c > > > index 440e73e1b11b..f2398749103b 100644 > > > --- a/kernel/bpf/fixups.c > > > +++ b/kernel/bpf/fixups.c > > > @@ -1817,6 +1817,43 @@ int bpf_do_misc_fixups(struct bpf_verifier_env= *env) > > > =C2=A0 goto next_insn; > > > =C2=A0 } > > > =C2=A0 > > > + if (bpf_jit_supports_percpu_insn() && > > > + =C2=A0=C2=A0=C2=A0 insn->code =3D=3D (BPF_LD | BPF_IMM | BPF_DW) &= & > > > + =C2=A0=C2=A0=C2=A0 (insn->src_reg =3D=3D BPF_PSEUDO_MAP_VALUE || > > > + =C2=A0=C2=A0=C2=A0=C2=A0 insn->src_reg =3D=3D BPF_PSEUDO_MAP_IDX_V= ALUE)) { > > > + struct bpf_map *map; > > > + > > > + aux =3D &env->insn_aux_data[i + delta]; > > > + map =3D env->used_maps[aux->map_index]; > > > + if (map->map_type !=3D BPF_MAP_TYPE_PERCPU_ARRAY) > > > + goto next_insn; > > > + > > > + prog->jit_required =3D true; > > > + > > > + /* > > > + * We are *skipping* first half of ld_imm64 insn > > > + * with 'i++;', patching over second half of it > > > + * with that same half + mov64_percpu_reg insn. > > > + * All because bpf_patch_insn_data() can only > > > + * replace one 8-byte insn, which does not work > > > + * well for ld_imm64 insn. > > > + */ > > > + > > > + insn_buf[0] =3D insn[1]; > > > + insn_buf[1] =3D BPF_MOV64_PERCPU_REG(insn->dst_reg, insn->dst_reg= ); > > > + cnt =3D 2; > >=20 > > Hi Leon, > >=20 > > Sorry for joining the discussion so late, but Andrii asked me to take > > a look at the verifier part of the changes. Could you please elaborate > > on what exactly does not work with 16-byte instructions and > > bpf_patch_insn_data()? Note that e.g. 'if (insn->imm =3D=3D BPF_FUNC_ti= mer_set_callback) {' > > case in the same bpf_do_misc_fixups() applies a patch containing BPF_LD= _IMM64(). >=20 > The BPF_FUNC_timer_set_callback case is different from this patch. >=20 > The BPF_FUNC_timer_set_callback case inserts a ld_imm64 insn at the > position of the call insn. >=20 > However, this patch is going to insert a mov64_percpu_reg insn after the > ld_imm64 insn. >=20 > Since ld_imm64 insn is a 16-byte insn, the new mov64_percpu_reg must sit > after the ld_imm64 insn by 'i++'. >=20 > Then, let's look into bpf_patch_insn_data(). bpf_patch_insn_data() > utilizes bpf_patch_insn_single() to insert insns at the position of one > 8-byte insn. See memmove(..., + off + 1, ...), the *1* is for one 8-byte > insn. I tried to modify bpf_patch_insn_single() to add 16-byte insn > support, but that looked much complicated against this patch. Ok, I see, it splits the original 16-byte instruction and moves the second half after the last patch instruction. Thank you for explaining. Acked-by: Eduard Zingerman