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Mon, 14 Sep 2026 06:36:44 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id sZ/NOPyVp2qAFgAAD6G6ig (envelope-from ); Mon, 14 Sep 2026 06:36:44 +0000 Message-ID: Date: Mon, 14 Sep 2026 08:36:44 +0200 X-Mailing-List: linux-aspeed@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/aspeed: Balance the display clock enable on teardown To: Myeonghun Pak , Joel Stanley Cc: Maarten Lankhorst , Maxime Ripard , David Airlie , Simona Vetter , Andrew Jeffery , Ryan Chen , Billy Tsai , Sam Ravnborg , =?UTF-8?Q?Noralf_Tr=C3=B8nnes?= , linux-aspeed@lists.ozlabs.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Ijae Kim References: <20260913223019.89651-1-mhun512@gmail.com> Content-Language: en-US From: Thomas Zimmermann Autocrypt: addr=tzimmermann@suse.de; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-4.30 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_TLS_ALL(0.00)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[16]; FREEMAIL_TO(0.00)[gmail.com,jms.id.au]; ARC_NA(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; FROM_HAS_DN(0.00)[]; FREEMAIL_CC(0.00)[linux.intel.com,kernel.org,gmail.com,ffwll.ch,codeconstruct.com.au,aspeedtech.com,ravnborg.org,tronnes.org,lists.ozlabs.org,lists.freedesktop.org,lists.infradead.org,vger.kernel.org]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.de:email,suse.de:mid,suse.com:url,imap1.dmz-prg2.suse.org:helo] Am 14.09.26 um 00:30 schrieb Myeonghun Pak: > aspeed_gfx_load() enables the display clock without checking the return > value and never disables it on probe failure or removal. devm_clk_get() > only releases the clock reference, leaving the enable unbalanced. > > Use devm_clk_get_enabled() to handle enable failures and automatically > disable and unprepare the clock on probe failure or removal. > > This issue was identified during our ongoing static-analysis research > while reviewing kernel code. > > Fixes: 4f2a8f5898ec ("drm: Add ASPEED GFX driver") > Co-developed-by: Ijae Kim > Signed-off-by: Ijae Kim > Signed-off-by: Myeonghun Pak > Assisted-by: OpenAI:GPT-5.6 Reviewed-by: Thomas Zimmermann > --- > Validated with an ARM64 W=1 object build and strict checkpatch. > No hardware runtime, clock-failure injection or unbind testing was done. > > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c > index d4577663a..aa36b79d0 100644 > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c > @@ -189,13 +189,12 @@ static int aspeed_gfx_load(struct drm_device *drm) > } > reset_control_deassert(priv->rst); > > - priv->clk = devm_clk_get(drm->dev, NULL); > + priv->clk = devm_clk_get_enabled(drm->dev, NULL); > if (IS_ERR(priv->clk)) { > dev_err(&pdev->dev, > - "missing or invalid clk device tree entry"); > + "failed to get and enable clock\n"); > return PTR_ERR(priv->clk); > } > - clk_prepare_enable(priv->clk); > > /* Sanitize control registers */ > writel(0, priv->base + CRT_CTRL1); -- -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstr. 146, 90461 Nürnberg, Germany, www.suse.com GF: Jochen Jaser, Andrew McDonald, (HRB 36809, AG Nürnberg)