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X-CSE-ConnectionGUID: /dK0gpr8TyaOY1YW0PuvCA== X-CSE-MsgGUID: HDyfk02/RWixwGAcpzixpQ== X-IronPort-AV: E=McAfee;i="6800,10657,11900"; a="93140419" X-IronPort-AV: E=Sophos;i="6.25,271,1779174000"; d="scan'208";a="93140419" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 19:54:17 -0700 X-CSE-ConnectionGUID: mEJEYVcrTHChDWvBhq++4g== X-CSE-MsgGUID: Rhzhej6vTyC+A5EngLnXQw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,271,1779174000"; d="scan'208";a="309749712" Received: from unknown (HELO [10.238.2.139]) ([10.238.2.139]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Sep 2026 19:54:15 -0700 Message-ID: Date: Thu, 10 Sep 2026 10:54:12 +0800 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/4] KVM: TDX: Validate directly configurable CPUID bits To: Artem Bityutskiy , "Edgecombe, Rick P" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" Cc: "Gao, Chao" , "seanjc@google.com" , "dave.hansen@linux.intel.com" , "kas@kernel.org" , "Li, Xiaoyao" , "pbonzini@redhat.com" , "andrew.cooper3@citrix.com" , "nik.borisov@suse.com" References: <20260827031837.2863609-1-binbin.wu@linux.intel.com> <32b51faabf60f6e87d9fdebbf2c3fe5a45fbff1c.camel@gmail.com> <58c185c82658819454a9950f37c6424226a098bb.camel@intel.com> <5faff363852572d59e34c876173d73c93734bd3c.camel@gmail.com> <473c5507-045f-454c-b6d1-76d2a390f413@linux.intel.com> Content-Language: en-US From: Binbin Wu In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/9/2026 7:20 PM, Artem Bityutskiy wrote: > On Wed, 2026-09-09 at 16:48 +0800, Binbin Wu wrote: >>> VMX: >>> VM entry = load guest state from guest-state area >>> VM exit = save guest state into guest-state area, >>> load host state from host-state area >>> >>> TDX: >>> SEAMCALL = save host state into SEAM VMCS guest-state area, >>> load module state from SEAM VMCS host-state area >>> SEAMRET = restore host state from SEAM VMCS guest-state area >>> >>> I may be reading the SDM wrong, let me know. >> >> That's my understanding too. > > Good, thanks for confirming. > >>> >>> So there are differences, and I was hoping to: >>> - Be corrected if I misinterpret the SDM and how things work. >>> - Get comments on whether the proposal took this into account. >>> - Get comments on how this affects, or does not affect, the proposal. >> >> For host state clobbering behavior, we cares about the values of the host (VMX >> root mode) after SEAMRET. >> >> When there is a control/field for "load host state from host-state area", I >> think there are two cases: >> - If there is the corresponding control/field for "load guest state from >> guest-state area", the TDX module could leverage it. >> - If there is no such corresponding control/field for "load guest state from >> guest-state area", the TDX module could do it in software way to mimic it. >> >> So from the view of the VMM, it can have the aligned behavior on host state >> clobbering behavior. > > Now I see what you mean: make msr_preservation.pdf follow the same rule > as the VMX host-state restore, and let the TDX module help where HW behaves > differently (call this SW restore vs HW restore via VMCS). > > That sounds good to me. > > My only doubt is whether it can be guaranteed in every case. A HW restore > happens after a SW restore. > > E.g., IA32_DEBUGCTL - HW clears it on VM exit (SDM 30.5.1), so whatever > TDX module puts there on the exit path, will be overwritten. Not that this > is an issue today, just using this as an example. But SEAMRET is actually a VM Entry, I think these special cases are during VM Exit. For a VM entry, the TDX module should be able to set whatever valid values for host. > > But I'd guess there would be only few problematic cases (if any). > > Then you wrote this: > > > FRED is a useful concrete example. Under VMX, the FRED host state in > IA32_FRED_CONFIG, IA32_FRED_STKLVLS, IA32_FRED_RSP1-3 and > IA32_FRED_SSP1-3 is covered by the VMCS host-state area, so the TDX module > is expected to restore these MSRs on TDH.VP.ENTER return. IA32_FRED_RSP0 > and IA32_PL0_SSP (a.k.a. IA32_FRED_SSP0) are handled by software, so the > TDX module is expected to clobber them on TDH.VP.ENTER return. > > > That one reads as obviously right to me. If VMX and TDX differed in how > IA32_FRED_RSP0 and IA32_PL0_SSP are handled, that would be a red flag. > > Did you go through all the MSRs and check that the VMX and TDX behavior > matches today? Not yet. This topic is put in the cover letter for discussions. And the patch series itself doesn't depend on conclusion of the discussions. > > Thanks!