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From: Miles Glenn To: Chinmay Rath , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, harshpb@linux.ibm.com Cc: npiggin@gmail.com, richard.henderson@linaro.org, vishalc@linux.ibm.com, tshah@linux.ibm.com, shivangu@linux.ibm.com, ojaswin@linux.ibm.com, aboorvad@linux.ibm.com, amachhiw@linux.ibm.com, sv@linux.ibm.com, shivani@linux.ibm.com, mkchauras@gmail.com, uverma@linux.ibm.com, nikhilks@linux.ibm.com Date: Mon, 24 Aug 2026 10:18:20 -0500 In-Reply-To: <20260820140114.327023-22-rathc@linux.ibm.com> References: <20260820140114.327023-1-rathc@linux.ibm.com> <20260820140114.327023-22-rathc@linux.ibm.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: KagtGOdZ4Te_8RMR1oyIHp4PzVUsWbit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDEyNiBTYWx0ZWRfXx9lsxqFwFlIL 5FjjnbftHbxJZjFK6UW6TDqo+Tx7pft6wqvjHYgHXJxaAAyXPwYT2tkrQgUvws6dN+ykc1sNb2X PQoMWvJ7G23G5hyA9YgK72QX+0IHfVmo3YGEukQiXCjUU1KHysLFK/Gh8wIuoliXW+dB9AFnQVD PDlCsqvOdhwuMdTF5AiN/zzw2RCHHNzYgKD36Z8Xnmic3/qLYbhzwcCSuid3M5qI27yyYlz0wpx gvfhiuSSHQ5fx1nxCVQ9xj/BaSeMG93cHbEMWR18JuLEUiGo8UEUNGgC+wS4ZCft9ro/t/Vbxsv tbrUzHXcJGRgFAY6g16Zq/sDjfdRCuNVYWqzXE43z9a32R+3BdUz4EGi/qi0mBLVzxSpPbFtmfj wy32ctrDnMZuYSqTNpOz3IqLTRcjT3PILxiJWCH2fLTLbC0qUoNu8jlQZz36S1zwrmmIA86drka 0Onx+D9hAlPEAGDltWw== X-Authority-Analysis: v=2.4 cv=Y/nIdBeN c=1 sm=1 tr=0 ts=6a8c60c1 cx=c_pps a=5BHTudwdYE3Te8bg5FgnPg==:117 a=5BHTudwdYE3Te8bg5FgnPg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=uQATh4VuCaFWsuC2iroA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDEyNiBTYWx0ZWRfX+FtslbfpH8Lr 4zO7ka3/1JO3yujw5p4PEyD/fMGCXDc5oxeZGHgtQsVY3Cyw56U6IIobOzGFRAfhTF9rj/SRv2E vIA79EnVkiv2gkbgO1flLJyAenTS760= X-Proofpoint-ORIG-GUID: 2zF0S6WVH7dBJ5hjVUSQL4LzfQcmNTHE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_04,2026-08-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240126 Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles Thanks, Glenn On Thu, 2026-08-20 at 19:30 +0530, Chinmay Rath wrote: > From: Shivang Upadhyay > > Move below instructions to decodetree specification : > > cr{and, or, xor, nand, nor, eqv, andc, orc} : XL-form > > The changes were verified by validating that the tcg ops generated by > those instructions remain the same, which were captured with the '-d > in_asm,op' flag. > > Signed-off-by: Shivang Upadhyay > Signed-off-by: Chinmay Rath > --- > target/ppc/insn32.decode | 11 ++++ > target/ppc/translate.c | 59 ---------------------- > target/ppc/translate/fixedpoint-impl.c.inc | 45 +++++++++++++++++ > 3 files changed, 56 insertions(+), 59 deletions(-) > > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index dc708b5442..a3973e042d 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -516,6 +516,17 @@ CFUGED 011111 ..... ..... ..... 0011011100 - @X > PDEPD 011111 ..... ..... ..... 0010011100 - @X > PEXTD 011111 ..... ..... ..... 0010111100 - @X > > +## Condition Register Instructions > + > +CRAND 010011 ..... ..... ..... 0100000001 - @X > +CROR 010011 ..... ..... ..... 0111000001 - @X > +CRNAND 010011 ..... ..... ..... 0011100001 - @X > +CRXOR 010011 ..... ..... ..... 0011000001 - @X > +CRNOR 010011 ..... ..... ..... 0000100001 - @X > +CREQV 010011 ..... ..... ..... 0100100001 - @X > +CRANDC 010011 ..... ..... ..... 0010000001 - @X > +CRORC 010011 ..... ..... ..... 0110100001 - @X > + > # Fixed-Point Hash Instructions > > HASHST 011111 ..... ..... ..... 1011010010 . @X_DW > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index d01981de73..5b08d9b282 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -2920,53 +2920,6 @@ static inline void gen_setlr(DisasContext *ctx, target_ulong nip) > tcg_gen_movi_tl(cpu_lr, nip); > } > > -/*** Condition register logical ***/ > -#define GEN_CRLOGIC(name, tcg_op, opc) \ > -static void glue(gen_, name)(DisasContext *ctx) \ > -{ \ > - uint8_t bitmask; \ > - int sh; \ > - TCGv_i32 t0, t1; \ > - sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ > - t0 = tcg_temp_new_i32(); \ > - if (sh > 0) \ > - tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ > - else if (sh < 0) \ > - tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ > - else \ > - tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ > - t1 = tcg_temp_new_i32(); \ > - sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ > - if (sh > 0) \ > - tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ > - else if (sh < 0) \ > - tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ > - else \ > - tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ > - tcg_op(t0, t0, t1); \ > - bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ > - tcg_gen_andi_i32(t0, t0, bitmask); \ > - tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ > - tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ > -} > - > -/* crand */ > -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); > -/* crandc */ > -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); > -/* creqv */ > -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); > -/* crnand */ > -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); > -/* crnor */ > -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); > -/* cror */ > -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); > -/* crorc */ > -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); > -/* crxor */ > -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); > - > /*** System linkage ***/ > > /* rfi (supervisor only) */ > @@ -5120,18 +5073,6 @@ GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) > GEN_STEPX(std, DEF_MEMOP(MO_UQ), 0x1D, 0x04) > #endif > > -#undef GEN_CRLOGIC > -#define GEN_CRLOGIC(name, tcg_op, opc) \ > -GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) > -GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), > -GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), > -GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), > -GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), > -GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), > -GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), > -GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), > -GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), > - > #undef GEN_MAC_HANDLER > #define GEN_MAC_HANDLER(name, opc2, opc3) \ > GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) > diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc > index d768a0454d..26b308e435 100644 > --- a/target/ppc/translate/fixedpoint-impl.c.inc > +++ b/target/ppc/translate/fixedpoint-impl.c.inc > @@ -540,6 +540,51 @@ static bool trans_MFCR(DisasContext *ctx, arg_MFCR *a) > return true; > } > > +static bool cr_logic_common(DisasContext *ctx, arg_X *a, > + void (*tcg_op)(TCGv_i32, TCGv_i32, TCGv_i32)) > +{ > + > + uint8_t bitmask; > + int sh; > + TCGv_i32 t0, t1; > + sh = (a->rt & 0x03) - (a->ra & 0x03); > + t0 = tcg_temp_new_i32(); > + if (sh > 0) { > + tcg_gen_shri_i32(t0, cpu_crf[a->ra >> 2], sh); > + } else if (sh < 0) { > + tcg_gen_shli_i32(t0, cpu_crf[a->ra >> 2], -sh); > + } else { > + tcg_gen_mov_i32(t0, cpu_crf[a->ra >> 2]); > + } > + > + t1 = tcg_temp_new_i32(); > + sh = (a->rt & 0x03) - (a->rb & 0x03); > + if (sh > 0) { > + tcg_gen_shri_i32(t1, cpu_crf[a->rb >> 2], sh); > + } else if (sh < 0) { > + tcg_gen_shli_i32(t1, cpu_crf[a->rb >> 2], -sh); > + } else { > + tcg_gen_mov_i32(t1, cpu_crf[a->rb >> 2]); > + } > + tcg_op(t0, t0, t1); > + > + bitmask = 0x08 >> (a->rt & 0x03); > + tcg_gen_andi_i32(t0, t0, bitmask); > + tcg_gen_andi_i32(t1, cpu_crf[a->rt >> 2], ~bitmask); > + tcg_gen_or_i32(cpu_crf[a->rt >> 2], t0, t1); > + > + return true; > +} > + > +TRANS(CRAND, cr_logic_common, tcg_gen_and_i32); > +TRANS(CROR, cr_logic_common, tcg_gen_or_i32); > +TRANS(CRXOR, cr_logic_common, tcg_gen_xor_i32); > +TRANS(CRNAND, cr_logic_common, tcg_gen_nand_i32); > +TRANS(CRNOR, cr_logic_common, tcg_gen_nor_i32); > +TRANS(CRANDC, cr_logic_common, tcg_gen_andc_i32); > +TRANS(CREQV, cr_logic_common, tcg_gen_eqv_i32); > +TRANS(CRORC, cr_logic_common, tcg_gen_orc_i32); > + > static bool do_add_D(DisasContext *ctx, arg_D *a, bool add_ca, bool compute_ca, > bool compute_ov, bool compute_rc0) > {